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US Patent 11476200 Semiconductor package structure having stacked die structure
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Patent
Current Assignee
Nanya Technology
Date Filed
June 27, 2019
Date of Patent
October 18, 2022
Patent Applicant
Nanya Technology
Patent Application Number
16454609
Patent Citations
US Patent 10128212 Semiconductor package and fabrication method thereof
US Patent 10593637 Multi-device packages and related microelectronic devices
US Patent 10964666 Chip on package structure and method
US Patent 10217720 Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US Patent 10347574 Integrated fan-out packages
US Patent 10522470 Package structure and method of fabricating the same
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11476200
Patent Primary Examiner
Ida M. Soward
CPC Code
H01L 23/5386
H01L 24/19
H01L 24/20
H01L 25/0652
H01L 25/18
H01L 25/043
H01L 25/0657
H01L 25/074
H01L 25/0756
H01L 25/071
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