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US Patent 11669957 Semiconductor wafer measurement method and system
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Current Assignee
Taiwan Semiconductor Manufacturing Company
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Date Filed
July 16, 2021
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Date of Patent
June 6, 2023
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Patent Applicant
Taiwan Semiconductor Manufacturing Company
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Patent Application Number
17377746
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Patent Citations
US Patent 7805018 Dynamic detection of blocking artifacts
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US Patent 7978902 Calibration method, inspection method, and semiconductor device manufacturing method
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US Patent 8046726 Waiver mechanism for physical verification of system designs
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US Patent 8111900 Computer-implemented methods for detecting and/or sorting defects in a design pattern of a reticle
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US Patent 8737676 Defect estimation device and method and inspection system and method
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US Patent 9097989 Target and method for mask-to-wafer CD, pattern placement and overlay measurement and control
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US Patent 9535015 Pattern inspection method and pattern inspection apparatus
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US Patent 9703919 System and method of filtering actual defects from defect information for a wafer
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US Patent 10318700 Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization
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US Patent 10818001 Using stochastic failure metrics in semiconductor manufacturing
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•••
Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11669957
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Patent Primary Examiner
Irfan Habib
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CPC Code
G06T 7/001
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