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US Patent 11764189 Molded direct bonded and interconnected stack

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
September 24, 2021
Date of Patent
September 19, 2023
Patent Application Number
17448794
Patent Citations
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US Patent 8802538 Methods for hybrid wafer bonding
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US Patent 10879212 Processed stacked dies
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US Patent 10879226 Stacked dies and methods for forming bonded structures
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US Patent 10886177 3D chip with shared clock distribution network
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US Patent 10892246 Structures and methods for low temperature bonding using nanoparticles
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US Patent 10923413 Hard IP blocks with physically bidirectional passageways
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US Patent 10950547 Stacked IC structure with system level wiring on multiple sides of the IC die
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US Patent 10964664 DBI to Si bonding for simplified handle wafer
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US Patent 10985133 Die processing
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US Patent 10991804 Transistor level interconnection methodologies utilizing 3D interconnects
•••
Patent Citations Received
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US Patent 12113056 Stacked dies and methods for forming bonded structures
0
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US Patent 11955463 Direct bonded stack structures for increased reliability and improved yield in microelectronics
0
Patent Inventor Names
Rajesh Katkar
Belgacem Haba
Guilian Gao
Cyprian Emeka Uzoh
Jeremy Alfred Theil
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11764189
Patent Primary Examiner
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Jose R Diaz
CPC Code
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H01L 25/0652
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H01L 25/071
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H01L 25/112
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H01L 24/95
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H01L 23/5386
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H01L 23/5385
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H01L 23/5384
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H01L 21/76898
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H01L 23/3135
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H01L 25/0657

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