US Patent 11854928 Semiconductor package and manufacturing method thereof

A semiconductor package includes an integrated circuit (IC) structure, an insulating encapsulation laterally covering the IC structure, and a redistribution structure disposed on the insulating encapsulation and the IC structure. The redistribution structure is electrically connected to the IC structure. The IC structure includes a first die, a capacitor structure, a dielectric layer laterally covering the first die and the capacitor structure, and a second die disposed on the dielectric layer, the first die, and the capacitor structure. The second die interacts with the capacitor structure, where a bonding interface between the second die and the first die is substantially coplanar with a bonding interface between the second die and the dielectric layer. A manufacturing method of a semiconductor package is also provided.