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US Patent 11862602 Scalable architecture for reduced cycles across SOC

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
November 7, 2019
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Date of Patent
January 2, 2024
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Patent Application Number
16677213
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Patent Citations
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US Patent 11176450 Three dimensional circuit implementing machine trained network
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US Patent 11355404 Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
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US Patent 11355443 Dielets on flexible and stretchable packaging for microelectronics
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US Patent 11367652 Microelectronic assembly from processed substrate
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US Patent 11373963 Protective elements for bonded structures
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US Patent 11380597 Bonded structures
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US Patent 11385278 Security circuitry for bonded structures
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US Patent 11387202 Nanowire bonding interconnect for fine-pitch microelectronics
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US Patent 11387214 Multi-chip modules formed using wafer-level processing of a reconstituted wafer
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US Patent 11393779 Large metal pads over TSV
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•••
Patent Citations Received
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US Patent 11990436 Electronic circuit for a hybrid molecular bonding
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Patent Inventor Names
Javier A. Delacruz
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Richard E. Perego
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11862602
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Patent Primary Examiner
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Sheng-Bai Zhu
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CPC Code
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H01L 23/528
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H01L 2224/32225
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H01L 23/00
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H01L 24/33
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H01L 25/0652
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H01L 23/481
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