US Patent 11908791 Partial subtractive supervia enabling hyper-scaling
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US Patent 11908791 Partial subtractive supervia enabling hyper-scaling
Article
Patent abstract
A semiconductor device includes an upper section of a supervia formed via subtractive etching and a lower section of the supervia formed via damascene processing. The supervia connects non-adjacent interconnect wiring. The lower section and the upper section of the supervia each define a generally cone-shaped configuration. A distal end of the lower section of the supervia is non-obtuse. Moreover, the lower section of the supervia is formed in a V
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Patent Number
Patent Inventor Names
Nicholas Anthony Lanzillo0
Sagarika Mukesh0
Date of Patent
February 20, 2024
0Patent Application Number
175323100
Date Filed
November 22, 2021
0Patent Citations
0
Patent Primary Examiner
CPC Code
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