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US Patent 11908791 Partial subtractive supervia enabling hyper-scaling

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
November 22, 2021
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Date of Patent
February 20, 2024
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Patent Application Number
17532310
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Patent Citations
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US Patent 10546772 Self-aligned via below subtractively patterned interconnect
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US Patent 10177031 Subtractive etch interconnects
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US Patent 10283407 Two-dimensional self-aligned super via integration on self-aligned gate contact
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US Patent 8357609 Dual damascene-like subtractive metal etch scheme
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US Patent 9502350 Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer
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US Patent 9601426 Interconnect structure having subtractive etch feature and damascene feature
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US Patent 9786597 Self-aligned pitch split for unidirectional metal wiring
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US Patent 9887133 Two-dimensional self-aligned super via integration on self-aligned gate contact
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US Patent 10020254 Integration of super via structure in BEOL
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US Patent 10026687 Metal interconnects for super (skip) via integration
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Patent Inventor Names
Sagarika Mukesh
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Nicholas Anthony Lanzillo
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11908791
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Patent Primary Examiner
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Tu-Tu V Ho
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CPC Code
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H01L 21/76804
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H01L 23/5226
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