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US Patent 11948926 Integrated circuit package and method

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
June 30, 2022
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Date of Patent
April 2, 2024
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Patent Application Number
17854386
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Patent Citations
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US Patent 8703542 Wafer-level packaging mechanisms
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US Patent 8759964 Wafer level package structure and fabrication methods
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US Patent 8778738 Packaged semiconductor devices and packaging devices and methods
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US Patent 8785299 Package with a fan-out structure and method of forming the same
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US Patent 8803306 Fan-out package structure and methods for forming the same
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US Patent 8809996 Package with passive devices and method of forming the same
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US Patent 8829676 Interconnect structure for wafer level package
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US Patent 8877554 Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
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US Patent 10522449 Packages with Si-substrate-free interposer and method forming same
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US Patent 10290611 Semiconductor packages and methods of forming same
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•••
Patent Inventor Names
Wei Ling Chang
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Chieh-Yen Chen
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Chuei-Tang Wang
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Chen-Hua Yu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11948926
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Patent Primary Examiner
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Fernando L Toledo
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CPC Code
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H01L 2924/12
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H01L 2924/1431
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H01L 2924/1434
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H01L 24/27
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H01L 24/19
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H01L 25/16
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H01L 24/20
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H01L 24/29
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