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US Patent 11973058 Multiple die assembly

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
November 25, 2021
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Date of Patent
April 30, 2024
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Patent Application Number
17535664
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Patent Citations
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US Patent 9520333 Wafer level package and fabrication method thereof
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US Patent 9860996 Selective area heating for 3D chip stack
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US Patent 9875986 Micro-scrub process for fluxless micro-bump bonding
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US Patent 9935090 Substrate design for semiconductor packages and method of forming same
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US Patent 10049953 Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
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US Patent 10541156 Multi integrated circuit chip carrier package
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US Patent 10269767 Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
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US Patent 10764996 Chip package assembly with composite stiffener
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US Patent 8389337 Patch on interposer assembly and structures formed thereby
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US Patent 9373559 Low-stress dual underfill packaging
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Patent Inventor Names
Katsuyuki Sakuma
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John Knickerbocker
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Mukta Ghate Farooq
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11973058
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Patent Primary Examiner
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Thao P. Le
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CPC Code
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H01L 23/36
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H01L 23/5383
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H01L 21/568
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H01L 25/0655
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H01L 21/561
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H01L 23/053
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