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US Patent 12002799 Die stacking structure and method forming same

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
July 25, 2022
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Date of Patent
June 4, 2024
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Patent Application Number
17814766
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Patent Citations
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US Patent 9293442 Semiconductor package and method
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US Patent 10014218 Method for forming semiconductor device structure with bumps
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US Patent 10529690 Package structures and methods of forming the same
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US Patent 10867874 Semiconductor device and method
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US Patent 10535633 Chip package having die structures of different heights and method of forming same
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US Patent 11037910 Semiconductor device having laterally offset stacked semiconductor dies
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US Patent 7843042 Wafer level integration package
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US Patent 8987057 Encapsulated wafer-level chip scale (WLSCP) pedestal packaging
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Patent Inventor Names
Cheng-Chieh Hsieh
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Ming Hung Tseng
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Hung-Yi Kuo
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Chung-Shi Liu
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Tsung-Yuan Yu
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Hao-Yi Tsai
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Chen-Hua Yu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12002799
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Patent Primary Examiner
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Anthony Ho
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CPC Code
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H01L 2224/97
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H01L 2924/181
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H01L 23/3128
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H01L 25/0657
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H01L 21/563
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