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US Patent 12087842 Inner spacer features for multi-gate transistors

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
June 16, 2023
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Date of Patent
September 10, 2024
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Patent Application Number
18336788
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Patent Citations
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US Patent 10290546 Threshold voltage adjustment for a gate-all-around semiconductor structure
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US Patent 10475902 Spacers for nanowire-based integrated circuit device and method of fabricating same
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US Patent 11289584 Inner spacer features for multi-gate transistors
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US Patent 10032627 Method for forming stacked nanowire transistors
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US Patent 10109721 Horizontal gate-all-around device having wrapped-around source and drain
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US Patent 10157799 Multi-gate device and method of fabrication thereof
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US Patent 10199502 Structure of S/D contact and method of making same
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US Patent 8963258 FinFET with bottom SiGe layer in source/drain
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US Patent 9818872 Multi-gate device and method of fabrication thereof
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US Patent 9887269 Multi-gate device and method of fabrication thereof
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•••
Patent Inventor Names
Bone-Fong Wu
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Chia-Pin Lin
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Chih-Hao Yu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12087842
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Patent Primary Examiner
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David C Spalla
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CPC Code
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H01L 29/775
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H01L 29/785
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H01L 29/7851
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H01L 29/7853
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H01L 2029/7858
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H01L 29/7855
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H01L 21/0214
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H01L 21/0228
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H01L 21/02603
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H01L 21/823431
0
•••

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