US Patent 12107126 Steep sloped vertical tunnel field-effect transistor
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US Patent 12107126 Steep sloped vertical tunnel field-effect transistor
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Patent abstract
The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.
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Patent Inventor Names
Matthias Passlack0
Peter Ramvall0
Date of Patent
October 1, 2024
0Patent Application Number
177479470
Date Filed
May 18, 2022
0Patent Citations
0
Patent Primary Examiner
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