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US Patent 12107126 Steep sloped vertical tunnel field-effect transistor

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
May 18, 2022
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Date of Patent
October 1, 2024
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Patent Application Number
17747947
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Patent Citations
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US Patent 9881993 Method of forming semiconductor structure with horizontal gate all around structure
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US Patent 9786774 Metal gate of gate-all-around transistor
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US Patent 9853101 Strained nanowire CMOS device and method of forming
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US Patent 9236267 Cut-mask patterning process for fin-like field effect transistor (FinFET) device
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US Patent 9502265 Vertical gate all around (VGAA) transistors and methods of forming the same
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US Patent 9520466 Vertical gate-all-around field effect transistors and methods of forming same
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US Patent 9520482 Method of cutting metal gate
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US Patent 9536738 Vertical gate all around (VGAA) devices and methods of manufacturing the same
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US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
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US Patent 9608116 FINFETs with wrap-around silicide and method forming the same
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Patent Inventor Names
Matthias Passlack
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Peter Ramvall
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12107126
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Patent Primary Examiner
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Moin M Rahman
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