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US Patent 8704364 Reducing stress in multi-die integrated circuit structures

Patent 8704364 was granted and assigned to Xilinx on April, 2014 by the United States Patent and Trademark Office.

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Patent Citations Received
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US Patent 11837581 Semiconductor package
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Patent abstract

An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.

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Patent Inventor Names
Bahareh Banijamali0
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=087043640
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Patent Citations Received
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US Patent 11664340 Negative fillet for mounting an integrated device die to a carrier
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US Patent 08704364 Reducing stress in multi-die integrated circuit structures US Patent 8704364 Reducing stress in multi-die integrated circuit structures

Infobox
Patent Number
087043640
Patent Number
87043640
Edits on 25 Apr, 2023
"Entity importer update"
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edited on 25 Apr, 2023
Infobox
Is a
Patent
Patent
0
Current Assignee
Xilinx
Xilinx
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
087043640
Date of Patent
April 22, 2014
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Patent Application Number
133692150
Date Filed
February 8, 2012
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=087043640
Patent Primary Examiner
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Hoang-Quan Ho
0
Edits on 19 Jun, 2022
"Entity importer update"
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edited on 19 Jun, 2022
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=08704364
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created this topic on 22 Dec, 2021
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 US Patent 08704364 Reducing stress in multi-die integrated circuit structures

Infobox
Is a
Patent
Patent
Current assignee
Xilinx
Xilinx
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
08704364
Date of patent
April 22, 2014
Patent application number
13369215
Date Filed
February 8, 2012
Patent primary examiner
‌
Hoang-Quan Ho

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