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Caridad Everhart

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Edits on 14 Dec, 2021
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7087521 Forming an intermediate layer in interconnect joints and structures formed thereby
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US Patent 7091598 Electronic circuit device
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US Patent 7094638 Method of forming gate structure
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US Patent 7098120 Method of manufacturing semiconductor devices
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US Patent 7098134 Method for fabricating semiconductor device
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US Patent 7101794 Coated semiconductor wafer, and process and device for producing the semiconductor wafer
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US Patent 7112507 MIM capacitor structure and method of fabrication
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US Patent 7112539 Dielectric layer for semiconductor device and method of manufacturing the same
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US Patent 7115524 Methods of processing a semiconductor substrate
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US Patent 7115525 Method for integrated circuit fabrication using pitch multiplication
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US Patent 7115534 Dielectric materials to prevent photoresist poisoning
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US Patent 7118941 Method of fabricating a composite carbon nanotube thermal interface device
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US Patent 7119032 Method to protect internal components of semiconductor processing equipment using layered superlattice materials
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US Patent 7122387 Deposition stop time detection apparatus and methods for fabricating copper wiring using the same
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US Patent 7125324 Insulated pad conditioner and method of using same
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US Patent 7129189 Aluminum phosphate incorporation in silica thin films produced by rapid surface catalyzed vapor deposition (RVD)
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US Patent 7132374 Method for depositing porous films
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US Patent 7135419 Line edge roughness reduction
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US Patent 7138281 Fabrication method of multisensors chips for detecting analytes
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US Patent 7138341 Process for making a memory structure
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US Patent 7141497 MOCVD apparatus and method
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US Patent 7141512 Method of cleaning semiconductor device fabrication apparatus
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US Patent 7144829 Method for fabricating semiconductor device and semiconductor substrate
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US Patent 7145246 Method of fabricating an ultra-narrow channel semiconductor device
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US Patent 7148080 Method for joining lead frames in a package assembly, method for forming a chip stack package, and a chip stack package
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US Patent 7148102 Methods of forming buried bit line DRAM circuitry
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US Patent 7148135 Method of designing low-power semiconductor integrated circuit
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US Patent 7148139 Method for forming metal wiring of semiconductor device
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US Patent 7148155 Sequential deposition/anneal film densification method
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US Patent 7151058 Etchant for etching nitride and method for removing a nitride layer using the same
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US Patent 7153785 Method of producing annealed wafer and annealed wafer
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US Patent 7161220 High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming same
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US Patent 7163848 Semiconductor device and manufacturing method thereof
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US Patent 7163899 Localized energy pulse rapid thermal anneal dielectric film densification method
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US Patent 7172910 Web fabrication of devices
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US Patent 7172947 High dielectric constant transition metal oxide materials
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US Patent 7172965 Method for manufacturing semiconductor device
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US Patent 7172972 Semiconductor device manufacture method and etching system
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US Patent 7176125 Method of forming a static random access memory with a buried local interconnect
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US Patent 7176136 Semiconductor device fabrication method
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US Patent 7179663 CDA controller and method for stabilizing dome temperature
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US Patent 7179698 Laser apparatus, laser annealing method, and manufacturing method of a semiconductor device
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US Patent 7179741 Electroless plating method and semiconductor wafer on which metal plating layer is formed
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US Patent 7179759 Barrier layer and fabrication method thereof
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US Patent 7183202 Method of forming metal wiring in a semiconductor device
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US Patent 7183224 Liftoff process for thin photoresist
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US Patent 7189626 Electroless plating of metal caps for chalcogenide-based memory devices
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US Patent 7192798 Fingerprint sensor apparatus and manufacturing method thereof
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US Patent 7192828 Capacitor with high dielectric constant materials and method of making
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US Patent 7192880 Method for line etch roughness (LER) reduction for low-k interconnect damascene trench etching
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US Patent 7192891 Method for forming a silicon oxide layer using spin-on glass
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US Patent 7196005 Dual damascene process with dummy features
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US Patent 7199059 Method for removing polymer as etching residue
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US Patent 7199063 Process for passivating polysilicon and process for fabricating polysilicon thin film transistor
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US Patent 7202182 Method of passivating oxide/compound semiconductor interface
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US Patent 7205242 Method for forming isolation layer in semiconductor device
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US Patent 7205247 Atomic layer deposition of hafnium-based high-k dielectric
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US Patent 7208427 Precursor compositions and processes for MOCVD of barrier materials in semiconductor manufacturing
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US Patent 7211497 Method for fabricating semiconductor devices
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US Patent 7211501 Method and apparatus for laser annealing
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US Patent 7214975 Semiconductor device with charge share countermeasure
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US Patent 7215027 Electrical coupling stack and processes for making same
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US Patent 7217325 System for processing a workpiece
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US Patent 7217618 Semiconductor device and method for fabricating the same using damascene process
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US Patent 7220321 Apparatus and processes for the mass production of photovoltaic modules
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US Patent 7220653 Plasma display panel and manufacturing method thereof
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US Patent 7220685 Method for depositing porous films
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US Patent 7229931 Oxygen plasma treatment for enhanced HDP-CVD gapfill
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US Patent 7229934 Porous organosilicates with improved mechanical properties
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US Patent 7232771 Method and apparatus for depositing charge and/or nanoparticles
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US Patent 7233066 Multilayer wiring substrate, and method of producing same
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US Patent 7235454 MIM capacitor structure and method of fabrication
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US Patent 7235497 Selective oxidation methods and transistor fabrication methods
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US Patent 7235500 Material for forming silica based film
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US Patent 7235837 Technique to control tunneling currents in DRAM capacitors, cells, and devices
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US Patent 7238576 Semiconductor device and method of manufacturing the same
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US Patent 7238605 Circuit structures and methods of forming circuit structures with minimal dielectric constant layers
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US Patent 7241633 Heat treatment apparatus and heat treatment method
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US Patent 7241635 Binning for semi-custom ASICs
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US Patent 7241689 Microprobe tips and methods for making
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US Patent 7241700 Methods for post offset spacer clean for improved selective epitaxy silicon growth
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US Patent 7241706 Low k ILD layer with a hydrophilic portion
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US Patent 7245029 Semiconductor device, manufacturing method and mounting method of the semiconductor device, circuit board, and electronic apparatus
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US Patent 7247574 Method and apparatus for providing optical proximity features to a reticle pattern for deep sub-wavelength optical lithography
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US Patent 7247577 Insulated pad conditioner and method of using same
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US Patent 7251374 System and method for hierarchical analysis of contrast enhanced medical imaging information
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US Patent 7253084 Deposition from liquid sources
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US Patent 7253123 Method for producing gate stack sidewall spacers
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US Patent 7256121 Contact resistance reduction by new barrier stack process
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US Patent 7256144 Method for forming a metal oxide film
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US Patent 7256499 Ultra low dielectric constant integrated circuit system
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US Patent 7259090 Copper damascene integration scheme for improved barrier layers
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US Patent 7259095 Semiconductor device and manufacturing process therefor as well as plating solution
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US Patent 7262142 Semiconductor device fabrication method
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US Patent 7265021 Alignment method, method for manufacturing a semiconductor device, substrate for a semiconductor device, electronic equipment
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US Patent 7268073 Post-polish treatment for inhibiting copper corrosion
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US Patent 7268078 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants
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US Patent 7271012 Failure analysis methods and systems
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US Patent 7271486 Retarding agglomeration of Ni monosilicide using Ni alloys
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US Patent 7273812 Microprobe tips and methods for making
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US Patent 7273818 Film formation method and apparatus for semiconductor process
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US Patent 7276423 III-nitride device and method with variable epitaxial growth direction
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US Patent 7276444 Method for processing interior of vapor phase deposition apparatus, method for depositing thin film and method for manufacturing semiconductor device
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US Patent 7276452 Method for removing mottled etch in semiconductor fabricating process
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US Patent 7276453 Methods for forming an undercut region and electronic devices incorporating the same
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US Patent 7282444 Semiconductor chip and manufacturing method for the same, and semiconductor device
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US Patent 7294573 Method for controlling poly 1 thickness and uniformity in a memory array fabrication process
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US Patent 7294574 Sputter deposition and etching of metallization seed layer for overhang and sidewall improvement
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US Patent 7294583 Methods for the use of alkoxysilanol precursors for vapor deposition of SiO
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US Patent 7294587 Component built-in module and method for producing the same
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US Patent 7300877 Method of manufacturing a semiconductor device
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US Patent 7304323 Test mask structure
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US Patent 7306965 Oxygen ion conductor device, method for fabricating oxygen ion conductor device, and oxygen concentration control system
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US Patent 7306977 Method and apparatus for facilitating signal routing within a programmable logic device
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US Patent 7309650 Memory device having a nanocrystal charge storage region and method
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US Patent 7309661 Method for forming gate of semiconductor device
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US Patent 7314824 Nitrogen-free ARC/capping layer and method of manufacturing the same
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US Patent 7316934 Personalized hardware
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US Patent 7320937 Method of reliably electroless-plating integrated circuit die
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US Patent 7323411 Method of selective tungsten deposition on a silicon surface
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US Patent 7323771 Electronic circuit device
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US Patent 7329613 Structure and method for forming semiconductor wiring levels using atomic layer deposition
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US Patent 7332435 Silicide structure for ultra-shallow junction for MOS devices
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US Patent 7335590 Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby
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US Patent 7335594 Method for manufacturing a memory device having a nanocrystal charge storage region
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US Patent 7335610 Ultraviolet blocking layer
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US Patent RE40137 Methods for forming integrated circuits within substrates
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US Patent 7338909 Micro-etching method to replicate alignment marks for semiconductor wafer photolithography
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US Patent 7341882 Method for forming an opto-electronic device
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US Patent 7341927 Wafer bonded epitaxial templates for silicon heterostructures
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US Patent 7341943 Post etch copper cleaning using dry plasma
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US Patent 7344979 High pressure treatment for improved grain growth and void reduction
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US Patent 7344994 Multiple layer etch stop and etching method
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US Patent 7354872 Hi-K dielectric layer deposition methods
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US Patent 7358119 Thin array plastic package without die attach pad and process for fabricating the same
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US Patent 7358181 Method for structuring a semiconductor device
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US Patent 7361588 Etch process for CD reduction of arc material
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US Patent 7361598 Method for fabricating semiconductor device capable of preventing scratch
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US Patent 7371694 Semiconductor device fabrication method and fabrication apparatus
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US Patent 7375024 Method for fabricating metal interconnection line with use of barrier metal layer formed in low temperature
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US Patent 7381642 Top layers of metal for integrated circuits
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US Patent 7396777 Method of fabricating high-k dielectric layer having reduced impurity
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US Patent 7399708 Method of treating a composite spin-on glass/anti-reflective material prior to cleaning
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US Patent 7413914 Method and apparatus for manufacturing semiconductor device, method and apparatus for controlling the same, and method and apparatus for simulating manufacturing process of semiconductor device
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US Patent 7485575 Method of manufacturing semiconductor device
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US Patent 8012842 Method for fabricating isolated integrated semiconductor structures
Edits on 13 Dec, 2021
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edited on 13 Dec, 2021
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US Patent 8012842 Method for fabricating isolated integrated semiconductor structures
Edits on 1 Dec, 2021
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Golden AI
edited on 1 Dec, 2021
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US Patent 7485575 Method of manufacturing semiconductor device
Edits on 1 Dec, 2021
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edited on 1 Dec, 2021
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edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7399708 Method of treating a composite spin-on glass/anti-reflective material prior to cleaning
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7396777 Method of fabricating high-k dielectric layer having reduced impurity
Edits on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7381642 Top layers of metal for integrated circuits
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edited on 29 Nov, 2021
Edits on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
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US Patent 7371694 Semiconductor device fabrication method and fabrication apparatus
Edits on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
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Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7361598 Method for fabricating semiconductor device capable of preventing scratch
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7361588 Etch process for CD reduction of arc material
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7358181 Method for structuring a semiconductor device
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7358119 Thin array plastic package without die attach pad and process for fabricating the same
Edits on 25 Nov, 2021
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7354872 Hi-K dielectric layer deposition methods
Edits on 24 Nov, 2021
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Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7344994 Multiple layer etch stop and etching method
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Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7344979 High pressure treatment for improved grain growth and void reduction
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7341943 Post etch copper cleaning using dry plasma
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7341927 Wafer bonded epitaxial templates for silicon heterostructures
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7341882 Method for forming an opto-electronic device
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Golden AI
edited on 23 Nov, 2021

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