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Sun James Lin

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Edits on 14 Dec, 2021
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7089512 Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits
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US Patent 7089513 Integrated circuit design for signal integrity, avoiding well proximity effects
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US Patent 7089515 Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power
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US Patent 7089516 Measurement of integrated circuit interconnect process parameters
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US Patent 7089527 Structures and methods for selectively applying a well bias to portions of a programmable device
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US Patent 7093204 Method and apparatus for automated synthesis of multi-channel circuits
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US Patent 7093226 Method and apparatus of wafer print simulation using hybrid model with mask optical images
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US Patent 7096435 Method and apparatus for detecting the type of interface to which a peripheral device is connected
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US Patent 7096439 System and method for performing intellectual property merge
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US Patent 7096441 Method for generating a command file of a group of DRC rules and/or a command file of a group of LVS/LPE rules
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US Patent 7100129 Hierarchical gcell method and mechanism
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US Patent 7103855 Clock control circuit and method
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US Patent 7107557 Method for calculation of cell delay time and method for layout optimization of semiconductor integrated circuit
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US Patent 7111256 Use of overlay diagnostics for enhanced automatic process control
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US Patent 7114134 Automatic circuit design method with a cell library providing transistor size information
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US Patent 7114138 Method and apparatus for extracting resistance from an integrated circuit design
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US Patent 7114143 Process yield learning
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US Patent 7117463 Verification of digital circuitry using range generators
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US Patent 7117475 Method and system for utilizing an isofocal contour to perform optical and process corrections
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US Patent 7120891 Master slice semiconductor integrated circuit
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US Patent 7120894 Pass-transistor logic circuit and a method of designing thereof
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US Patent 7124378 Material estimation apparatus, material estimation program and method of estimating materials
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US Patent 7124381 Method of estimating crosstalk noise in lumped RLC coupled interconnects
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US Patent 7124384 Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor
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US Patent 7124386 Dummy fill for integrated circuits
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US Patent 7127693 Device for creating timing constraints
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US Patent 7127698 Method for reducing reticle set cost
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US Patent 7131079 Method of generating protected standard delay format file
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US Patent 7131104 Fast and accurate optical proximity correction engine for incorporating long range flare effects
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US Patent 7131106 Integrated circuit pattern designing method, exposure mask manufacturing method, exposure mask, and integrated circuit device manufacturing method
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US Patent 7134106 Method and system for providing fast design for testability prototyping in integrated circuit designs
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US Patent 11177412 Sputter deposition apparatus including roller assembly and method
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US Patent 7137078 Trace based method for design navigation
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US Patent 7137087 Integrated circuit verification scheme
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US Patent 7137088 System and method for determining signal coupling coefficients for lines
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US Patent 7139985 Development system for an integrated circuit having standardized hardware objects
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US Patent 7139988 Modeling metastability in circuit design
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US Patent 7139997 Method and system for checking operation of a mask generation algorithm
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US Patent 7143370 Parameter linking system for data visualization in integrated circuit technology development
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US Patent 7143383 Method for layout of gridless non manhattan integrated circuits with tile based router
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US Patent 7146580 Interchangeable integrated circuit building blocks
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US Patent 7146586 System and method for automated electronic device design
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US Patent 7146590 Congestion estimation for programmable logic devices
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US Patent 7149999 Method for correcting a mask design layout
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US Patent 7159199 Method for verifying adequate synchronization of signals that cross clock environments and system
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US Patent 7165229 Generating optimized and secure IP cores
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US Patent 7165230 Switch methodology for mask-programmable logic devices
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US Patent 7168054 Software traffic generator/analyzer
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US Patent 7171633 Estimating quality during early synthesis
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US Patent 7178114 Scripted, hierarchical template-based IC physical layout system
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US Patent 7181713 Static timing and risk analysis tool
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US Patent 7181715 Method and system for supporting circuit design for products
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US Patent 7181720 Process and device for circuit design by means of high-level synthesis
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US Patent 7181722 Method of dividing circuit pattern, method of manufacturing stencil mask, stencil mask and method of exposure
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US Patent 7185293 Universal hardware device and method and tools for use therewith
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US Patent 7185302 Method for generating layouts by chamfering corners of polygons
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US Patent 7185308 Correlation of behavioral HDL signals
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US Patent 7188323 Restricted scan reordering technique to enhance delay fault coverage
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US Patent 7188324 Assertion morphing in functional verification of integrated circuit design
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US Patent 7188330 Handling of unused coreware with embedded boundary scan chains to avoid the need of a boundary scan synthesis tool during custom instance creation
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US Patent 7191423 Method and apparatus for folding and laying out electronic circuit
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US Patent 7194710 Scheduling events in a boolean satisfiability (SAT) solver
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US Patent 7194719 Basic cell, edge cell, wiring shape, wiring method, and shield wiring structure
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US Patent 7197723 Semiconductor device manufacturing
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US Patent 7197728 Method for setting design margin for LSI
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US Patent 7200822 Circuits with modular redundancy and methods and apparatuses for their automated synthesis
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US Patent 7200830 Enhanced electrically-aligned proximity communication
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US Patent 7207018 Method and apparatus for locating short circuit faults in an integrated circuit layout
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US Patent 7210115 Methods for optimizing programmable logic device performance by reducing congestion
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US Patent 7213219 Function verification method
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US Patent 7213220 Method for verification of gate level netlists using colored bits
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US Patent 7216322 Clock tree synthesis for low power consumption and low clock skew
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US Patent 7225421 Clock tree distribution generation by determining allowed placement regions for clocked elements
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US Patent 7228512 Method of generating capacitance value rule table for extraction of wiring capacitance and capacitance value rule table generation program
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US Patent 7228523 Method of automatically correcting mask pattern data and program for the same
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US Patent 7231625 Method and apparatus for use of hidden decoupling capacitors in an integrated circuit design
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US Patent 7240304 Method for voltage drop analysis in integreted circuits
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US Patent 7240314 Redundantly tied metal fill for IR-drop and layout density optimization
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US Patent 7240317 Placement/net wiring processing system
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US Patent 7240318 Placement/net wiring processing system
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US Patent 7240319 Apparatus, system, method, and program for facilitating the design of bare circuit boards
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US Patent 7243318 Integrated test processor (ITP) for a system on chip (SOC) that includes a network on chip (NOC)
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US Patent 7243320 Stochastic analysis process optimization for integrated circuit design and manufacture
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US Patent 7243325 Method and apparatus for generating a wafer map
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US Patent 7246340 Timing-driven synthesis with area trade-off
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US Patent 7249336 Automatic wiring method for semiconductor integrated circuit, program for the same, and semiconductor integrated circuit
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US Patent 7249339 Method and apparatus for optimizing delay paths through field programmable gate arrays
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US Patent 7249341 Synthesis of cyclic combinational circuits
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US Patent 7251792 Net list creating method, net list creating device, and computer program thereof
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US Patent 7251800 Method and apparatus for automated circuit design
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US Patent 7254798 Method and apparatus for designing integrated circuit layouts
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US Patent 7257790 Layout structure of semiconductor integrated circuit and method for forming the same
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US Patent 7260801 Delay computation speed up and incrementality
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US Patent 7260813 Method and apparatus for photomask image registration
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US Patent 7263683 Simplified optical proximity correction based on 1-dimension versus 2-dimension pattern shape classification
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US Patent 7266788 Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules
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US Patent 7266800 Method and system for designing manufacturable patterns that account for the pattern- and position-dependent nature of patterning processes
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US Patent 7266803 Layout generation and optimization to improve photolithographic performance
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US Patent 7269810 Global equivalent circuit modeling system for substrate mounted circuit components incorporating substrate dependent characteristics
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US Patent 7272813 Transparent re-mapping of parallel computational units
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US Patent 7272814 Reconfiguring a RAM to a ROM using layers of metallization
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US Patent 7275225 Correcting design data for manufacture
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US Patent 7275229 Auto connection assignment system and method
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US Patent 7275231 High level validation of designs and products
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US Patent 7278124 Design method for semiconductor integrated circuit suppressing power supply noise
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US Patent 7281226 Incrementally resolved phase-shift conflicts in layouts for phase-shifted features
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US Patent 7284211 Extensible IO testing implementation
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US Patent 7284217 Method of LSI designing and a computer program for designing LSIS
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US Patent 7284222 Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit
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US Patent 7284230 System for search and analysis of systematic defects in integrated circuits
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US Patent 7287236 Electronic device connectivity analysis methods and systems
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US Patent 7290235 Method and system for embedding wire model objects in a circuit schematic design
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US Patent 7290240 Leveraging combinations of synthesis, placement and incremental optimizations
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US Patent 7299446 Enabling efficient design reuse in platform ASICs
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US Patent 7305651 Mask CD correction based on global pattern density
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US Patent 7308658 Method and apparatus for measuring test coverage
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US Patent 7310789 Use of overlay diagnostics for enhanced automatic process control
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US Patent 7310791 Method for correcting layout errors
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US Patent 7310797 Method and system for printing lithographic images with multiple exposures
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US Patent 7313770 MOSFET modeling for IC design accurate for high frequencies
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US Patent 7315996 Method and system for performing heuristic constraint simplification
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US Patent 7318211 Method for physical placement of an integrated circuit based on timing constraints
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US Patent 7331029 Method and system for enhancing circuit design process
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US Patent 7334198 Software controlled transistor body bias
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US Patent 7337414 Logical equivalence verifying device, method, and computer-readable medium thereof
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US Patent 7340696 Automated design process and chip description system
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US Patent 7340701 Layout verification method and device
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US Patent 7340708 Method and apparatus for generating layout pattern
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US Patent 7343569 Apparatus and method for reset distribution
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US Patent 7343578 Method and system for generating a bitstream view of a design
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US Patent 7346886 Method and apparatus for determining chip arrangement position on substrate
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US Patent 7350163 System and method for automatically calculating parameters of an MOSFET
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US Patent 7353470 Variable clocked scan test improvements
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US Patent 7353472 System and method for testing pattern sensitive algorithms for semiconductor design
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US Patent 7353482 Routing display facilitating task of removing error
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US Patent 7356795 Semiconductor integrated circuit device and method for designing the same
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US Patent 7356798 Semiconductor integrated circuit routing method and recording medium which stores routing software
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US Patent 7360182 Method and system for reducing delay noise in an integrated circuit
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US Patent 7360187 Mixed mode verifier
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US Patent 7363605 Eliminating false positives in crosstalk noise analysis
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US Patent 7367008 Adjustment of masks for integrated circuit fabrication
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US Patent 7370313 Method for optimizing a photolithographic mask
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US Patent 7373618 Method and system for selection and replacement of subcircuits in equivalence checking
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US Patent 7376928 Basic cell, edge cell, wiring shape, wiring method, and shield wiring structure
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US Patent 7380232 Method and apparatus for designing a system for implementation in a programmable logic device
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US Patent 7389482 Method and apparatus for analyzing post-layout timing violations
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US Patent 7398493 Isolated pwell tank verification using node breakers
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US Patent 7398494 Method for performing verification of logic circuits
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US Patent 7398499 Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design
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US Patent 7398509 Network-based photomask data entry interface and instruction generator for manufacturing photomasks
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US Patent 7409651 Automated migration of analog and mixed-signal VLSI design
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US Patent 7409654 Method and apparatus for performing test pattern autograding
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US Patent 7923058 Method for manufacturing carbon fibers and method for manufacturing electron emitting device using the same, method for manufacturing display, and ink for producing catalyst for use in these methods
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US Patent 7923061 Method of manufacturing safety cones from recycled materials
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US Patent 7998526 Method and system for dynamic in-situ phosphor mixing and jetting
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US Patent 8012526 Electroluminescent element and manufacturing method thereof
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US Patent 8012527 Manufacturing method of display device and display device therefrom
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US Patent 8012528 Composition for conductive materials comprising tetra acrylate functionalised arylamines, conductive material and layer, electronic device and equipment
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US Patent 8012529 Light emitting element and manufacturing method thereof
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US Patent 8012530 Organic thin-film photoelectric conversion element and method of manufacturing the same
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US Patent 8012531 Solar cell and method for manufacturing the same, and method for forming impurity region
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US Patent 8012537 Controlling the vaporization of organic material
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US Patent 8012545 Film forming method, film forming apparatus, method of manufacturing device, and apparatus for manufacturing device
Edits on 13 Dec, 2021
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Golden AI
edited on 13 Dec, 2021
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Golden AI
edited on 13 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 8012537 Controlling the vaporization of organic material
Golden AI profile picture
Golden AI
edited on 13 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8012529 Light emitting element and manufacturing method thereof
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Golden AI
edited on 13 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8012531 Solar cell and method for manufacturing the same, and method for forming impurity region
Golden AI profile picture
Golden AI
edited on 13 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8012530 Organic thin-film photoelectric conversion element and method of manufacturing the same
Golden AI profile picture
Golden AI
edited on 13 Dec, 2021
Golden AI profile picture
Golden AI
edited on 13 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 8012527 Manufacturing method of display device and display device therefrom
Golden AI profile picture
Golden AI
edited on 13 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 8012526 Electroluminescent element and manufacturing method thereof
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7998526 Method and system for dynamic in-situ phosphor mixing and jetting
Edits on 7 Dec, 2021
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7923061 Method of manufacturing safety cones from recycled materials
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Golden AI
edited on 7 Dec, 2021
Edits on 1 Dec, 2021
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Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7409654 Method and apparatus for performing test pattern autograding
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Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7409651 Automated migration of analog and mixed-signal VLSI design
Edits on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7398494 Method for performing verification of logic circuits
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7398493 Isolated pwell tank verification using node breakers
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7389482 Method and apparatus for analyzing post-layout timing violations
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Golden AI
edited on 30 Nov, 2021

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