US Patent 10522642 Semiconductor device with air-spacer

A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.