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US Patent 11423966 Memory array staircase structure

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
October 27, 2020
Date of Patent
August 23, 2022
Patent Application Number
17081380
Patent Citations
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US Patent 10446437 Interlevel connectors in multilevel circuitry, and method for forming the same
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US Patent 10256248 Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof
0
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US Patent 10115681 Compact three-dimensional memory device having a seal ring and methods of manufacturing the same
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US Patent 10109639 Lateral non-volatile storage cell
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US Patent 10593399 Self-selecting memory array with horizontal bit lines
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US Patent 10930333 Embedded ferroelectric memory cell
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Patent Citations Received
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US Patent 12087621 Air gaps in memory array structures
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US Patent 11776602 Memory array staircase structure
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US Patent 11985825 3D memory array contact structures
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US Patent 11985830 Three-dimensional memory device and method
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US Patent 12002534 Memory array word line routing
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US Patent 12022659 Three-dimensional memory device and method
0
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US Patent 11716856 Three-dimensional memory device and method
0
Patent Inventor Names
Han-Jong Chia
0
Feng-Cheng Yang
0
Chung-Te Lin
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Yu-Ming Lin
0
Sheng-Chen Wang
0
Meng-Han Lin
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11423966
Patent Primary Examiner
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Fernando Hidalgo
CPC Code
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H01L 27/11551
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H01L 27/1159
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H01L 29/6684
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H01L 29/78391
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G11C 8/14
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H01L 21/8221
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H01L 27/1052
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H01L 21/8239
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H01L 27/11597
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H01L 27/11578

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