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US Patent 11664286 Method for forming package structure

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Date Filed
July 12, 2021
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Date of Patent
May 30, 2023
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Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Application Number
17372814
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Patent Citations
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US Patent 9461018 Fan-out PoP structure with inconsecutive polymer layer
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US Patent 9496189 Stacked semiconductor devices and methods of forming same
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US Patent 9666502 Discrete polymer in fan-out packages
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US Patent 10347562 Methods and structures for increasing the allowable die size in TMV packages
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US Patent 9735131 Multi-stack package-on-package structures
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US Patent 8993380 Structure and method for 3D IC package
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US Patent 9281254 Methods of forming integrated circuit package
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US Patent 9372206 Testing of semiconductor chips with microbumps
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US Patent 9425126 Dummy structure for chip-on-wafer-on-substrate
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US Patent 9443783 3DIC stacking device and method of manufacture
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11664286
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Patent Primary Examiner
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Peniel M Gumedzoe
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CPC Code
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H01L 21/565
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H01L 24/81
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