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US Patent 11764171 Integrated circuit structure and method
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Patent
Date Filed
April 27, 2021
Date of Patent
September 19, 2023
Patent Application Number
17241715
Patent Citations
US Patent 9425126 Dummy structure for chip-on-wafer-on-substrate
US Patent 9443783 3DIC stacking device and method of manufacture
US Patent 9461018 Fan-out PoP structure with inconsecutive polymer layer
US Patent 9496189 Stacked semiconductor devices and methods of forming same
US Patent 9666502 Discrete polymer in fan-out packages
US Patent 9735131 Multi-stack package-on-package structures
US Patent 10867879 Integrated circuit package and method
US Patent 8993380 Structure and method for 3D IC package
US Patent 10978392 Electrical chip and optical module
US Patent 9281254 Methods of forming integrated circuit package
•••
Patent Inventor Names
Kuo Lung Pan
Hao-Yi Tsai
Chen-Hua Yu
Tin-Hao Kuo
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11764171
Patent Primary Examiner
Kyoung Lee
CPC Code
H01L 2224/18
H01L 21/4853
H01L 21/4857
H01L 21/565
H01L 21/568
H01L 21/6835
H01L 23/3128
H01L 23/645
H01L 23/5383
H01L 23/5386
•••
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