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US Patent 12079475 Ferroelectric memory chiplet in a multi-dimensional packaging

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
April 13, 2021
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Date of Patent
September 3, 2024
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Patent Application Number
17229743
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Patent Citations
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US Patent 7683459 Bonding method for through-silicon-via based 3D wafer stacking
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US Patent 8143710 Wafer-level chip-on-chip package, package on package, and methods of manufacturing the same
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US Patent 8198716 Die backside wire bond technology for single or stacked die package
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US Patent 8525342 Dual-side interconnected CMOS for stacked integrated circuits
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US Patent 8546955 Multi-die stack package
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US Patent 8547769 Energy efficient power distribution for 3D integrated circuit stack
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US Patent 8612809 Systems, methods, and apparatuses for stacked memory
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US Patent 8701073 System and method for across-chip thermal and power management in stacked IC designs
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US Patent 8759899 Integration of 3D stacked IC device with peripheral circuits
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US Patent 9165968 3D-stacked backside illuminated image sensor and method of making the same
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•••
Patent Inventor Names
Rajeev Kumar Dokania
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Debo Olaosebikan
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Sasikanth Manipatruni
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Christopher B. Wilkerson
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Amrita Mathuriya
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12079475
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Patent Primary Examiner
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Christine A Enad
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CPC Code
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G06N 20/00
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G06F 3/061
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G06F 3/0655
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H01L 23/49811
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H01L 25/0657
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H01L 23/49894
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G06F 3/0679
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