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David E. Graybill

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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Infobox (-170 properties)
Infobox
Patent primary examiner of
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US Patent 7087442 Process for the formation of a spatial chip arrangement and spatial chip arrangement
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US Patent 7087465 Method of packaging a semiconductor light emitting device
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US Patent 7091571 Image sensor package and method for manufacture thereof
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US Patent 7098078 Microelectronic component and assembly having leads with offset portions
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US Patent 7098091 Method for fabricating thin film transistors
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US Patent 7102216 Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
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US Patent 7105380 Method of temporarily securing a die to a burn-in carrier
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US Patent 7105386 High density SRAM cell with latched vertical transistors
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US Patent 7105858 Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density
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US Patent 7109064 Method of forming a semiconductor package and leadframe therefor
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US Patent 7109573 Thermally enhanced component substrate
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US Patent 7112528 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
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US Patent 7115976 Method and apparatus for epoxy LOC die attachment
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US Patent 7115977 Multi-chip package type semiconductor device
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US Patent 7125740 Solid-state image pickup device and fabrication method thereof
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US Patent 7126154 Test structure for a single-sided buried strap DRAM memory cell array
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US Patent 11177373 Method for manufacturing semiconductor device
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US Patent 11177437 Alignment through topography on intermediate component for memory device patterning
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US Patent 7141448 Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials
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US Patent 7144748 Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density
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US Patent 7145175 Semiconductor circuit and method of fabricating the same
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US Patent 7148503 Semiconductor device, function setting method thereof, and evaluation method thereof
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US Patent 7151277 Selective etching of silicon carbide films
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US Patent 7157320 Semiconductor device and process of production of same
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US Patent 7157742 Integrated circuit device
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US Patent 7157787 Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
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US Patent 7160771 Forming gate oxides having multiple thicknesses
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US Patent 7161211 Aluminum-containing film derived from using hydrogen and oxygen gas in sputter deposition
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US Patent 7166915 Multi-chip module system
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US Patent 7169643 Semiconductor device, method of fabricating the same, circuit board, and electronic apparatus
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US Patent 7172930 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer
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US Patent 7176462 Semiconductor device, and control method and device for driving unit component of semiconductor device
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US Patent 7180186 Ball grid array package
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US Patent 7183138 Method and apparatus for decoupling conductive portions of a microelectronic device package
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US Patent 7186646 Semiconductor devices and methods of forming a barrier metal in semiconductor devices
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US Patent 7195940 Methods for packaging image sensitive electronic devices
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US Patent 7196000 Method for manufacturing a wafer level chip scale package
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US Patent 7198969 Semiconductor chip assemblies, methods of making same and components for same
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US Patent 7202556 Semiconductor package having substrate with multi-layer metal bumps
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US Patent 7205170 Method for the production of LED bodies
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US Patent 7208828 Semiconductor package with wire bonded stacked dice and multi-layer metal bumps
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US Patent 7211289 Method of making multilayered printed circuit board with filled conductive holes
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US Patent 7214569 Apparatus incorporating small-feature-size and large-feature-size components and method for making same
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US Patent 7217578 Advanced process control of thermal oxidation processes, and systems for accomplishing same
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US Patent 7217606 Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures
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US Patent 7217999 Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semiconductor chip on the interconnection board
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US Patent 7220318 Semiconductor device manufacturing apparatus and semiconductor device manufacturing method
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US Patent 7224026 Nanoelectronic devices and circuits
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US Patent 7229861 Method for producing semiconductor device
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US Patent 7230263 Gallium nitride compound semiconductor element
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US Patent 7233056 Chip scale package with heat spreader
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US Patent 7243423 Chip package with degassing holes
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US Patent 7250330 Method of making an electronic package
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US Patent 7253034 Dual SIMOX hybrid orientation technology (HOT) substrates
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US Patent 7256069 Wafer-level package and methods of fabricating
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US Patent 7259043 Circular test pads on scribe street area
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US Patent 7259450 Double-packaged multi-chip semiconductor module
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US Patent 7265029 Fabrication of substrates with a useful layer of monocrystalline semiconductor material
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US Patent 7271038 Methods of forming ruthenium film by changing process conditions during chemical vapor deposition and ruthenium films formed thereby
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US Patent 7276386 Semiconductor device and method of manufacturing the same
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US Patent 7276394 Large area flat image sensor assembly
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US Patent 7279378 Method of fabricating isolated semiconductor devices in epi-less substrate
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US Patent 7279410 Method for forming inlaid structures for IC interconnections
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US Patent 7285764 Solid state imaging device and method of driving the same
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US Patent 7291385 Conductive film and method for preparing the same
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US Patent 7291910 Semiconductor chip assemblies, methods of making same and components for same
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US Patent 7298021 Electronic device and method for manufacturing the same
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US Patent 7300823 Apparatus for housing a micromechanical structure and method for producing the same
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US Patent 7318844 Laser-irradiated metallized electroceramic
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US Patent 7327035 System and method for providing a low frequency filter pole
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US Patent 7329564 Wafer dividing method
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US Patent 7331102 Apparatus for detecting an amount of strain and method for manufacturing same
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US Patent 7335517 Multichip semiconductor device, chip therefor and method of formation thereof
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US Patent 7335965 Packaging of electronic chips with air-bridge structures
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US Patent 7338843 Method for producing an electronic component, especially a memory chip
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US Patent 7338882 Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same
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US Patent 7348261 Wafer scale thin film package
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US Patent 7354798 Three-dimensional device fabrication method
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US Patent 7361540 Method of reducing noise disturbing a signal in an electronic device
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US Patent 7371624 Method of manufacturing thin film semiconductor device, thin film semiconductor device, electro-optical device, and electronic apparatus
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US Patent 7381573 Self-aligned, low-resistance, efficient memory array
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US Patent 7381604 Strained-channel semiconductor structure and method for fabricating the same
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US Patent 7381613 Self-aligned MIM capacitor process for embedded DRAM
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US Patent 7384799 Method to avoid amorphous-si damage during wet stripping processes in the manufacture of MEMS devices
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US Patent 7387902 Methods for packaging image sensitive electronic devices
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US Patent 7387912 Packaging of electronic chips with air-bridge structures
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US Patent 7388279 Tapered dielectric and conductor structures and applications thereof
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US Patent 7399399 Method for manufacturing semiconductor package substrate
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US Patent 7399671 Disposable pillars for contact formation
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US Patent 7399919 Flexible heat sink
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US Patent 7402182 High-power LGA socket
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US Patent 7402466 Strained silicon CMOS on hybrid crystal orientations
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US Patent 7410879 System and method for providing a dual via architecture for thin film resistors
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US Patent 7427537 Semiconductor integrated circuit device and method for manufacturing the same
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US Patent 7427548 Method for producing charge-trapping memory cell arrays
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US Patent 7435673 Methods of forming integrated circuit devices having metal interconnect structures therein
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US Patent 7445971 Thin film transistor and method for manufacturing the same
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US Patent 7445979 Method of fabricating isolated semiconductor devices in epi-less substrate
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US Patent 7446002 Method for making a semiconductor device comprising a superlattice dielectric interface layer
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US Patent 7446392 Electronic device and method for manufacturing the same
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US Patent 7463831 Transponder assembly for use with parallel optics modules in fiber optic communications systems
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US Patent 7465977 Method for producing a packaged integrated circuit
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US Patent 7466021 Memory packages having stair step interconnection layers
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US Patent 7485483 Methods of fabricating active device array substrate and fabricating color filter substrate
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US Patent 7485562 Method of making multichip wafer level packages and computing systems incorporating same
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US Patent 7495872 Semiconductor unit
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US Patent 7497905 Ternary nitride-based buffer layer of a nitride-based light-emitting device and a method for manufacturing the same
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US Patent 7498211 Independently controlled, double gate nanowire memory cell with self-aligned contacts
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US Patent 7500431 System, method, and apparatus for membrane, pad, and stamper architecture for uniform base layer and nanoimprinting pressure
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US Patent 7501592 Narrow weighing system arranged in narrowly spaced rows in the lateral direction
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US Patent 7511275 Semiconductor device, and control method and device for driving unit component of semiconductor device
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US Patent 11189573 Semiconductor package with electromagnetic interference shielding using metal layers and vias
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US Patent 7517740 Method of crystallizing/activating polysilicon layer and method of fabricating thin film transistor having the same polysilicon layer
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US Patent 7527658 Method of manufacturing displays and apparatus for manufacturing displays
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US Patent 7547579 Underfill process
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US Patent 7550314 Patterned plasma treatment to improve distribution of underfill material
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US Patent 7553719 Flash memory device and method for fabricating the same
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US Patent 7563696 Semiconductor device manufacturing apparatus and semiconductor device manufacturing method
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US Patent 7579218 Electronic assembly/system with reduced cost, mass, and volume and increased efficiency and power density
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US Patent 7586181 Semiconductor device and method for manufacturing
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US Patent 7592671 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer
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US Patent 7617769 System, method, and apparatus for membrane, pad, and stamper architecture for uniform base layer and nanoimprinting pressure
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US Patent 7704801 Resin for sealing semiconductor device, resin-sealed semiconductor device and the method of manufacturing the semiconductor device
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US Patent 7704812 Semiconductor circuit and method of fabricating the same
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US Patent 7709353 Method for producing semiconductor device
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US Patent 7709853 Packaged semiconductor light emitting devices having multiple optical elements
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US Patent 7714396 Metal-oxide semiconductor field effect transistor
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US Patent 7718001 Method for fabricating semiconductor epitaxial layers using metal islands
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US Patent 7759214 Semiconductor including STI and method for manufacturing the same
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US Patent 7767498 Encapsulated devices and method of making
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US Patent 7781240 Integrated circuit device
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US Patent 7781326 Formation of a tantalum-nitride layer
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US Patent 7790486 Light emitting device and method of manufacturing the same
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US Patent 7790574 Boron diffusion in silicon devices
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US Patent 7816271 Methods for forming contacts for dual stress liner CMOS semiconductor devices
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US Patent 7823595 Apparatus for etching substrate and method of fabricating thin-glass substrate
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US Patent 7829461 Method for fabricating semiconductor device
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US Patent 7829975 Multichip semiconductor device, chip therefor and method of formation thereof
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US Patent 7855147 Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer
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US Patent 7858514 Integrated circuit, intermediate structure and a method of fabricating a semiconductor structure
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US Patent 7859028 Independently controlled, double gate nanowire memory cell with self-aligned contacts
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US Patent 7863705 Semiconductor device having a bonding pad structure including an annular contact
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US Patent 7868336 Semiconductor device and method of manufacturing the same
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US Patent 7879694 System and method for applying a pre-gate plasma etch in a semiconductor device manufacturing process
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US Patent 7880301 Semiconductor device and method for manufacturing the same
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US Patent 7888172 Chip stacked structure and the forming method
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US Patent 7888235 Fabrication of substrates with a useful layer of monocrystalline semiconductor material
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US Patent 7902014 CMOS devices with a single work function gate electrode and method of fabrication
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US Patent 7902649 Leadframe for leadless package, structure and manufacturing method using the same
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US Patent 7906429 Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof
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US Patent 7915064 Processing for overcoming extreme topography
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US Patent 7927961 Selective etching method and method for forming an isolation structure of a memory device
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US Patent 7927983 Laser irradiation method, laser irradiation apparatus, and method of manufacturing a semiconductor device
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US Patent 7928424 Nitride-based light-emitting device
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US Patent 7932512 Implantation before epitaxial growth for photonic integrated circuits
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US Patent 7935565 Electronic devices
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US Patent 7935616 Dynamic p-n junction growth
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US Patent 7951622 Method of making a semiconductor chip assembly with a post/base heat spreader and a signal post
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US Patent 7960240 System and method for providing a dual via architecture for thin film resistors
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US Patent 7964428 Micromechanical component and method for fabricating a micromechanical component
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US Patent 7968394 Transistor with immersed contacts and methods of forming thereof
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US Patent 7973391 Tapered dielectric and conductor structures and applications thereof
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US Patent 7981702 Integrated circuit package in package system
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US Patent 7981809 Film formation method and apparatus for semiconductor process
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US Patent 7982217 Semiconductor device and its test method
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US Patent 7989338 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects
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US Patent 7993981 Electronic device package and method of manufacture
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US Patent 7998856 Interconnects with a dielectric sealant layer
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US Patent 8008130 Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board
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US Patent 8008183 Dual capillary IC wirebonding
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8008183 Dual capillary IC wirebonding
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Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7998856 Interconnects with a dielectric sealant layer
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7993981 Electronic device package and method of manufacture
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Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7982217 Semiconductor device and its test method
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7981809 Film formation method and apparatus for semiconductor process
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7981702 Integrated circuit package in package system
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7973391 Tapered dielectric and conductor structures and applications thereof
Edits on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7968394 Transistor with immersed contacts and methods of forming thereof
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7964428 Micromechanical component and method for fabricating a micromechanical component
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7960240 System and method for providing a dual via architecture for thin film resistors
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7935616 Dynamic p-n junction growth
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7935565 Electronic devices
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7932512 Implantation before epitaxial growth for photonic integrated circuits
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7928424 Nitride-based light-emitting device
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Golden AI
edited on 7 Dec, 2021
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Golden AI
edited on 7 Dec, 2021

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