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Helen Rossoshek

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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 11176308 Extracting parasitic capacitance from circuit designs
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US Patent 11177667 Viral distribution of battery management parameters
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US Patent 11182527 Cell placement site optimization
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US Patent 7380228 Method of associating timing violations with critical structures in an integrated circuit design
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US Patent 7426709 Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system
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US Patent 7444614 Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal
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US Patent 7451421 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies
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US Patent 7464352 Methods for designing, evaluating and manufacturing semiconductor devices
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US Patent 7464356 Method and apparatus for diffusion based cell placement migration
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US Patent 7475379 Methods and systems for layout and routing using alternating aperture phase shift masks
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US Patent 7478346 Debugging system for gate level IC designs
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US Patent 7478355 Input/output circuits with programmable option and related method
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US Patent 7480885 Method and apparatus for routing with independent goals on different layers
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US Patent 7487481 Receiver circuit for on chip timing adjustment
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US Patent 7493578 Correlation of data from design analysis tools with design blocks in a high-level modeling system
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US Patent 7496871 Mutual inductance extraction using dipole approximations
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US Patent 7496874 Semiconductor yield estimation
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US Patent 7500207 Influence-based circuit design
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US Patent 7500217 Handling of flat data for phase processing including growing shapes within bins to identify clusters
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US Patent 7506279 Design supporting apparatus capable of checking functional description of large-scale integrated circuit to detect fault in said circuit
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US Patent 7509594 Method of selling integrated circuit dies for multi-chip packages
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US Patent 7509596 Power distribution network simulation method using variable reduction method
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US Patent 7509599 Method and apparatus for performing formal verification using data-flow graphs
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US Patent 7509605 Extending incremental verification of circuit design to encompass verification restraints
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US Patent 7509607 Memory circuit having a crosstalk-glitch suppressor circuit and a control device for controlling an amount of suppression performed by the crosstalk-glitch suppressor circuit
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US Patent 7509618 Method and apparatus for facilitating an adaptive electronic design automation tool
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US Patent 7509619 Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages
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US Patent 7509623 Manufacturing method of semiconductor device
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US Patent 7512912 Method and apparatus for solving constraints for word-level networks
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US Patent 7512916 Electrostatic discharge testing method and semiconductor device fabrication method
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US Patent 7512918 Multimode delay analysis for simplifying integrated circuit design timing models
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US Patent 7512921 Method and apparatus for designing integrated circuit enabling the yield of integrated circuit to be improved by considering random errors
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US Patent 7512926 Phase-shifting masks with sub-wavelength diffractive optical elements
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US Patent 7516425 Method for generating minimal leakage current input vector using heuristics
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US Patent 7516430 Generating testcases based on numbers of testcases previously generated
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US Patent 11187992 Predictive modeling of metrology in semiconductor processes
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US Patent 11189639 Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped for mitigating electromigration
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US Patent 7523438 Method for improved lithographic patterning utilizing optimized illumination conditions and high transmission attenuated PSM
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US Patent 7536669 Generic DMA IP core interface for FPGA platform design
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US Patent 7539957 Automatic test pattern generation tool with feedback path capabilities for testing circuits with repeating blocks
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US Patent 7543249 Embedded switchable power ring
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US Patent 7543251 Method and apparatus replacing sub-networks within an IC design
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US Patent 7543253 Method and apparatus for compensating for temperature drift in semiconductor processes and circuitry
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US Patent 7546559 Method of optimization of clock gating in integrated circuit designs
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US Patent 7546568 Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage
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US Patent 7546571 Distributed electronic design automation environment
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US Patent 7581200 System and method for analyzing length differences in differential signal paths
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US Patent 7584447 PLD architecture for flexible placement of IP function blocks
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US Patent 7587693 Apparatus and method of delay calculation for structured ASIC
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US Patent 7590959 Layout system, layout program, and layout method for text or other layout elements along a grid
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US Patent 7596774 Hard macro with configurable side input/output terminals, for a subsystem
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US Patent 7600211 Toggle equivalence preserving logic synthesis
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US Patent 7603645 Calibration method of insulating washer in circuit board
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US Patent 7610569 Chip design verification apparatus and data communication method for the same
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US Patent 7617467 Electrostatic discharge device verification in an integrated circuit
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US Patent 7620926 Methods and structures for flexible power management in integrated circuits
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US Patent 7631286 Automated metrology recipe generation
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US Patent 7636902 Report validation tool
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US Patent 7640521 Model verification support method, apparatus, and computer-readable recording medium storing program
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US Patent 7640522 Method and system for placing layout objects in a standard-cell layout
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US Patent 7640526 Modular partial reconfiguration
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US Patent 7644389 Method for producing a mask for the lithographic projection of a pattern onto a substrate
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US Patent 7650588 Methods and systems for pattern generation based on multiple forms of design data
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US Patent 7665054 Optimizing circuit layouts by configuring rooms for placing devices
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US Patent 7669157 Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
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US Patent 7669169 Shape-based geometry engine to perform smoothing and other layout beautification operations
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US Patent 7676782 Efficient method for mapping a logic design on field programmable gate arrays
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US Patent 7681156 Transmission circuit simulator and transmission circuit simulation program storage medium
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US Patent 7681172 Method and apparatus for modeling an apodization effect in an optical lithography system
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US Patent 7685553 System and method for global circuit routing incorporating estimation of critical area estimate metrics
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US Patent 7685554 Determination of data rate and data type in a high-level electronic design
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US Patent 7689949 Evaluating Green's functions for modeling multilayer integrated circuits
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US Patent 7694259 Data models for describing an electrical device
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US Patent 7698664 Secure exchange of information in electronic design automation
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US Patent 7698674 System and method for efficient analysis of point-to-point delay constraints in static timing
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US Patent 7698680 Engineering change order cell and method for arranging and routing the same
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US Patent 7703064 Multilayered circuit board design support method, program, and apparatus for suppressing thermal diffusion from solid-layer conductor to through hole
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US Patent 7703066 Exposure mask manufacturing method, drawing apparatus, semiconductor device manufacturing method, and mask blanks product
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US Patent 7707524 Osculating models for predicting the operation of a circuit structure
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US Patent 7712064 Manufacturing aware design of integrated circuit layouts
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US Patent 7712070 Method for transferring self-assembled dummy pattern to substrate
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US Patent 7716626 Method of designing a circuit layout of a semiconductor device
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US Patent 7721234 Simulation method and simulation program
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US Patent 7725850 Methods for design rule checking with abstracted via obstructions
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US Patent 7725860 Contact mapping using channel routing
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US Patent 7725865 Method, storage media storing program, and component for avoiding increase in delay time in semiconductor circuit having plural wiring layers
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US Patent 7735034 Simulation model for a semiconductor device describing a quasi-static density of a carrier as a non-quasi-static model
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US Patent 7735056 Automated circuit design dimension change responsive to low contrast condition determination in photomask phase pattern
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US Patent 7739633 Verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling system and program product
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US Patent 7739638 Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium considering influence of signal input to peripheral circuit which does not have logical influence
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US Patent 7739651 Method and apparatus to determine if a pattern is robustly manufacturable
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US Patent 7752579 Film thickness predicting program, recording medium, film thickness predicting apparatus, and film thickness predicting method
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US Patent 7761821 Technology migration for integrated circuits with radical design restrictions
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US Patent 7761825 Generating testcases based on numbers of testcases previously generated
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US Patent 7761828 Partitioning electronic circuit designs into simulation-ready blocks
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US Patent 7765506 Method and apparatus for automated synthesis of multi-channel circuits
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US Patent 7765513 Configuration database supporting selective presentation of configuration entities
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US Patent 7770144 Modular array defined by standard cell logic
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US Patent 7779378 Computer program product for extending incremental verification of circuit design to encompass verification restraints
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US Patent 7779380 Data processing apparatus including reconfigurable logic circuit
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US Patent 7784015 Method for generating a mask layout and constructing an integrated circuit
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US Patent 7788617 Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis
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US Patent 7788630 Method and apparatus for determining an optical model that models the effect of optical proximity correction
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US Patent 7793243 Multi-engine static analysis
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US Patent 7793245 Statistical iterative timing analysis of circuits having latches and/or feedback loops
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US Patent 7793250 Topology-driven apparatus, method and computer program product for developing a wiring design
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US Patent 7797660 Semiconductor integrated circuit for controlling substrate bias
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US Patent 7797661 Method and apparatus for describing and managing properties of a transformer coil
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US Patent 7797668 Method for optimally converting a circuit design into a semiconductor device
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US Patent 7802219 Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout
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US Patent 7802222 Generalized constraint collection management method
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US Patent 7805698 Methods and systems for physical hierarchy configuration engine and graphical editor
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US Patent 7818693 Methodology for improving device performance prediction from effects of active area corner rounding
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US Patent 7818709 Circuit-pattern-data correction method and semiconductor-device manufacturing method
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US Patent 7818711 System and method for making photomasks
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US Patent 7823103 Method and system of introducing hierarchy into design rule checking test cases and rotation of test case data
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US Patent 7823108 Chip having timing analysis of paths performed within the chip during the design process
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US Patent 7823111 Semiconductor integrated circuit device, semiconductor integrated circuit design method, and semiconductor integrated circuit design apparatus
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US Patent 7823112 Method, software and system for ensuring timing between clocked components in a circuit
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US Patent 7827509 Digitally obtaining contours of fabricated polygons
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US Patent 7827512 Semiconductor device and method of designing the same
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US Patent 7827515 Package designs for fully functional and partially functional chips
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US Patent 7827517 Automated register definition, builder and integration framework
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US Patent 7827519 Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs
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US Patent 7831945 Manufacturing a clock distribution network in an integrated circuit
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US Patent 7831954 Flash-based updating techniques for high-accuracy high efficiency mask synthesis
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US Patent 7840918 Method and apparatus for physical implementation of a power optimized circuit design
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US Patent 7844932 Method to identify timing violations outside of manufacturing specification limits
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US Patent 7853911 Method and apparatus for performing path-level skew optimization and analysis for a logic design
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US Patent 7853912 Arrangements for developing integrated circuit designs
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US Patent 7853916 Methods of using one of a plurality of configuration bitstreams for an integrated circuit
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US Patent 7861193 Reuse of circuit labels for verification of circuit recognition
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US Patent 7861200 Setup and hold time characterization device and method
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US Patent 7865851 Capacitance extraction of intergrated circuits with floating fill
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US Patent 7870524 Method and system for automating unit performance testing in integrated circuit design
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US Patent 7873923 Power gating logic cones
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US Patent 7873934 Method and apparatus for implementing carry chains on field programmable gate array devices
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US Patent 7873936 Method for quantifying the manufactoring complexity of electrical designs
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US Patent 7877710 Method and apparatus for deriving signal activities for power analysis and optimization
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US Patent 7882474 Testing phase error of multiple on-die clocks
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US Patent 7886239 Phase coherent differtial structures
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US Patent 7895540 Multilayer finite difference methods for electrical modeling of packages and printed circuit boards
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US Patent 7900165 Determining a design attribute by estimation and by calibration of estimated value
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US Patent 7900166 Method to produce an electrical model of an integrated circuit substrate and related system and article of manufacture
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US Patent 7904843 Systematic generation of scenarios from specification sheet
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US Patent 7904847 CMOS circuit leakage current calculator
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US Patent 7913198 Method for designing array antennas
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US Patent 7921403 Controlling impedance and thickness variations for multilayer electronic structures
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US Patent 7926011 System and method of generating hierarchical block-level timing constraints from chip-level timing constraints
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US Patent 7926018 Method and apparatus for generating a layout for a transistor
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US Patent 7930666 System and method of providing a memory hierarchy
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US Patent 7934184 Integrated circuit design using modified cells
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US Patent 7937679 Method for performing failure mode and effects analysis of an integrated circuit and computer program product therefor
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US Patent 7941771 Method for functional verification of an integrated circuit model for constituting a verification platform, equipment emulator and verification platform
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US Patent 7945875 Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization using design compiler
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US Patent 7945878 Rules and directives for validating correct data used in the design of semiconductor products
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US Patent 7945880 Constraint based retiming of synchronous circuits
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US Patent 7949976 Systematic approach for performing cell replacement in a circuit to meet timing requirements
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US Patent 7954075 Vector sequence simplification for circuit verification
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US Patent 7962868 Method for forming a semiconductor device using optical proximity correction for the optical lithography
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US Patent 7962870 Prediction of dynamic current waveform and spectrum in a semiconductor device
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US Patent 7966588 Optimization of electrical circuits
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US Patent 7971173 Method and system for implementing partial reconfiguration and rip-up of routing
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US Patent 7979815 Compact model methodology for PC landing pad lithographic rounding impact on device performance
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US Patent 7984403 Verification supporting system
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US Patent 8001491 Organic thin film transistor and method of fabricating the same
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US Patent 8001495 System and method of predicting problematic areas for lithography in a circuit design
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US Patent 8001501 Method for circuit design
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US Patent 8001510 Automated method of architecture mapping selection from constrained high level language description via element characterization
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US Patent 8001511 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies
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US Patent 8010912 Method of shrinking semiconductor mask features for process improvement
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US Patent 8010923 Latch based optimization during implementation of circuit designs for programmable logic devices
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US Patent 8010927 Structure for a stacked power clamp having a BigFET gate pull-up circuit
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8010927 Structure for a stacked power clamp having a BigFET gate pull-up circuit
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8010912 Method of shrinking semiconductor mask features for process improvement
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Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8001491 Organic thin film transistor and method of fabricating the same
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8001501 Method for circuit design
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8001495 System and method of predicting problematic areas for lithography in a circuit design
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7984403 Verification supporting system
Edits on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7971173 Method and system for implementing partial reconfiguration and rip-up of routing
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7966588 Optimization of electrical circuits
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7962870 Prediction of dynamic current waveform and spectrum in a semiconductor device
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7954075 Vector sequence simplification for circuit verification
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Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7945880 Constraint based retiming of synchronous circuits

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