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Leigh M. Garbowski

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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7089510 Method and program product of level converter optimization
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US Patent 7093215 Semiconductor circuit device and circuit simulation method for the same
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US Patent 7093216 Apparatus connectable to a computer network for circuit design verification, computer implemented method for circuit design verification, and computer program product for controlling a computer system so as to verify circuit designs
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US Patent 7100140 Generation of graphical congestion data during placement driven synthesis optimization
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US Patent 7107570 Method and system for user-defined triggering logic in a hardware description language
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US Patent 7111260 System and method for incremental statistical timing analysis of digital circuits
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US Patent 7111270 Method and apparatus to adaptively validate a physical net routing topology of a substrate design
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US Patent 7117455 System and method for derivative-free optimization of electrical circuits
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US Patent 7117458 Identifying specific netlist gates for use in code coverage testing
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US Patent 7117461 Method of estimating performance of integrated circuit designs using state point identification
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US Patent 7124379 Method for communicating a measuring position of a structural element that is to be formed on a mask
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US Patent 7124389 Automated wiring pattern layout method
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US Patent 7124393 System and method for processing configuration information
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US Patent 7127690 Method and system for defect evaluation using quiescent power plane current (IDDQ) voltage linearity
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US Patent 7131083 Optimization of clock network capacitance on an integrated circuit
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US Patent 7131090 Clocked gating based on measured performance
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US Patent 7131100 Identifying phantom images generated by side-lobes
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US Patent 7134096 System and method for design, procurement and manufacturing collaboration
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US Patent 11176298 Method for modeling
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US Patent 11176300 Systems and methods for creating individualized processing chips and assemblies
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US Patent 11176309 System and method for validation of photonics device layout designs
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US Patent 7146599 Method for using asymmetric OPC structures on line ends of semiconductor pattern layers
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US Patent 7149986 Automated load determination for partitioned simulation
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US Patent 7152218 Behavioral synthesis system, behavioral synthesis method, control program, readable recording medium, logic circuit production method, and logic circuit
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US Patent 7155689 Design-manufacturing interface via a unified model
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US Patent 7155692 Method and system for performing timing analysis on a circuit
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US Patent 7162705 Dynamically reconfiguring clock domains on a chip
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US Patent 7168056 System and method for verifying trace distances of a PCB layout
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US Patent 7168058 Printed circuit wiring board designing support device, printed circuit board designing method, and its program
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US Patent 7171641 Voltage change reflecting delay calculation method, and voltage change reflecting delay calculation system
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US Patent 7174521 System and method for product yield prediction
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US Patent 7174526 Accurate density calculation with density views in layout databases
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US Patent 7178120 Method for performing timing closure on VLSI chips in a distributed environment
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US Patent 7178122 Semiconductor integrated circuit, method of designing semiconductor integrated circuit, and device for designing the same
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US Patent 7181721 Short edge management in rule based OPC
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US Patent 7185305 Creating a power distribution arrangement with tapered metal wires for a physical design
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US Patent 7188326 Methods for designing and testing semiconductor integrated circuits with plural clock groups
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US Patent 7191416 System and method for modifying integrated circuit hold times
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US Patent 7191427 Method for mapping a logic circuit to a programmable look up table (LUT)
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US Patent 7194706 Designing scan chains with specific parameter sensitivities to identify process defects
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US Patent 7194708 Generation of clock gating function for synchronous circuit
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US Patent 7194724 High level synthesis method and high level synthesis apparatus
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US Patent 7194725 System and method for design rule creation and selection
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US Patent 7197724 Modeling a logic design
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US Patent 7197734 Method and apparatus for designing systems using logic regions
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US Patent 7210112 Element placement method and apparatus
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US Patent 7210113 Process and apparatus for placing cells in an IC floorplan
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US Patent 7210114 Redistribution metal for output driver slew rate control
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US Patent 7213222 Method of HDL simulation considering hard macro core with negative setup/hold time
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US Patent 7216308 Method and apparatus for solving an optimization problem in an integrated circuit layout
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US Patent 7216326 Resource activity aware system for determining a resource interconnection pattern within an essentially digital device and devices created therewith
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US Patent 7219315 Comparison of semiconductor circuitry simulations
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US Patent 7219320 Semiconductor integrated circuit timing analysis apparatus timing analysis method and timing analysis program
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US Patent 7222318 Circuit optimization for minimum path timing violations
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US Patent 7222319 Timing analysis method and apparatus
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US Patent 7222326 Automatic process and design method, system and program product
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US Patent 7225423 Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks
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US Patent 7228509 Design tools for configurable serial communications protocols
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US Patent 7228517 Integrated circuit design method and system
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US Patent 7231623 Netlist database
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US Patent 7234125 Timing analysis for programmable logic
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US Patent 7234126 Task concurrency management design method
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US Patent 7234129 Calculating etch proximity-correction using object-precision techniques
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US Patent 7237212 Method and apparatus for reducing timing pessimism during static timing analysis
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US Patent 7240310 Method, system and program product for evaluating a circuit
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US Patent 7243326 Client-specific circuit board with isolated redundant systems
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US Patent 7246331 Method for optimizing integrated circuit device design and service
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US Patent 7246338 Method and apparatus for computing cost of a path expansion to a surface
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US Patent 7246343 Method for correcting position-dependent distortions in patterning of integrated circuits
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US Patent 7251795 Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design
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US Patent 7254792 Accounting for the effects of dummy metal patterns in integrated circuits
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US Patent 7254794 Timing performance analysis
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US Patent 7257781 Method, circuit library and computer program product for implementing enhanced performance and reduced leakage current for ASIC designs
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US Patent 7257795 Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints
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US Patent 7260791 Integrated circuit designing system, method and program
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US Patent 7260798 Compilation of remote procedure calls between a timed HDL model on a reconfigurable hardware platform and an untimed model on a sequential computing platform
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US Patent 7263679 Semiconductor integrated circuit device with boundary scan test and design automation apparatus, boundary scan test method and program
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US Patent 7266801 Design pattern correction method and mask pattern producing method
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US Patent 7269812 Apparatus and method for performing static timing analysis of an integrated circuit design
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US Patent 7269813 Off-width pitch for improved circuit card routing
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US Patent 7272810 Semiconductor integrated circuit having multi-level interconnection, CAD method and CAD tool for designing the semiconductor integrated circuit
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US Patent 7278126 Method and apparatus for fixing hold time violations in a circuit design
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US Patent 7290237 Method for programming a mask-programmable logic device and device so programmed
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US Patent 7290241 Method and system for managing behavior of algorithms
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US Patent 7296246 Multi-domain clock skew scheduling
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US Patent 7296251 Method of physical planning voltage islands for ASICs and system-on-chip designs
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US Patent 7299428 Model stamping matrix check technique in circuit simulator
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US Patent 7302663 Automatic antenna diode insertion for integrated circuits
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US Patent 7302665 Method and apparatus for designing a layout, and computer product
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US Patent 7308657 Method for generating hints for program analysis
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US Patent 7308661 Method and apparatus for characteristic impedance discontinuity reduction in high-speed flexible circuit applications
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US Patent 7310785 Video processing architecture definition by function graph methodology
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US Patent 7310790 Automatic symbolic indexing methods for formal verification on a symbolic lattice domain
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US Patent 7313775 Integrated circuit with relocatable processor hardmac
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US Patent 7313781 Image data correction method, lithography simulation method, image data correction system, program, mask and method of manufacturing a semiconductor device
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US Patent 7318208 Method for circuit sensitivity driven parasitic extraction
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US Patent 7318210 Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays
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US Patent 7318213 Apparatus, method and program for behavioral synthesis including loop processing
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US Patent 7325207 Automatic device strength based sensitization generation for sequential elements
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US Patent 7325221 Logic system with configurable interface
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US Patent 7325222 Method and apparatus for verifying the post-optical proximity corrected mask wafer image sensitivity to reticle manufacturing errors
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US Patent 7328415 Modeling blocks of an integrated circuit for timing verification
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US Patent 7337416 Method of using strongly coupled components to estimate integrated circuit performance
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US Patent 7340711 Method and apparatus for local preferred direction routing
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US Patent 7343577 Area array routing masks for improved escape of devices on PCB
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US Patent 7343582 Optical proximity correction using progressively smoothed mask shapes
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US Patent 7346870 System and method for verifying trace widths of a PCB layout
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US Patent 7346875 Wiring optimizations for power
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US Patent 7346879 Symmetric signal distribution through abutment connection
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US Patent RE40188 System and method for providing an integrated circuit with a unique identification
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US Patent 7353492 Method of IC fabrication, IC mask fabrication and program product therefor
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US Patent 7356786 Method and user interface for debugging an electronic system
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US Patent 7356788 Method and apparatus for data hierarchy maintenance in a system for mask description
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US Patent 7356800 System and method for product yield prediction
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US Patent 7360188 Method and apparatus for characteristics impedance discontinuity reduction in high-speed flexible circuit applications
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US Patent 7363599 Method and system for matching a hierarchical identifier
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US Patent 11182532 Hierarchical density uniformization for semiconductor feature surface planarization
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US Patent 7367005 Method and apparatus for designing a layout, and computer product
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US Patent 7370294 Design techniques for low leakage circuits based on delay statistics
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US Patent 7370299 Method and computer program product for register transfer level power estimation in chip design
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US Patent 7373625 System and method for product yield prediction
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US Patent 7392493 Techniques for super fast buffer insertion
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US Patent 11188705 Pin accessibility prediction engine
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US Patent 11189864 Electronic device and control method
Edits on 2 Dec, 2021
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edited on 2 Dec, 2021
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US Patent 11189864 Electronic device and control method
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Golden AI
edited on 2 Dec, 2021
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US Patent 11188705 Pin accessibility prediction engine
Edits on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
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US Patent 7392493 Techniques for super fast buffer insertion
Edits on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
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US Patent 7373625 System and method for product yield prediction
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edited on 26 Nov, 2021
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 7370294 Design techniques for low leakage circuits based on delay statistics
Edits on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7367005 Method and apparatus for designing a layout, and computer product
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Golden AI
edited on 25 Nov, 2021
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Infobox
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US Patent 11182532 Hierarchical density uniformization for semiconductor feature surface planarization
Edits on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
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Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7363599 Method and system for matching a hierarchical identifier
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Golden AI
edited on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
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US Patent 7356800 System and method for product yield prediction
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Golden AI
edited on 25 Nov, 2021
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Patent primary examiner of
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US Patent 7356788 Method and apparatus for data hierarchy maintenance in a system for mask description
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Golden AI
edited on 25 Nov, 2021
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Patent primary examiner of
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US Patent 7356786 Method and user interface for debugging an electronic system
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Golden AI
edited on 25 Nov, 2021
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US Patent 7353492 Method of IC fabrication, IC mask fabrication and program product therefor
Edits on 24 Nov, 2021
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Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent RE40188 System and method for providing an integrated circuit with a unique identification
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Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7346879 Symmetric signal distribution through abutment connection
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Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7346875 Wiring optimizations for power
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Golden AI
edited on 24 Nov, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7346870 System and method for verifying trace widths of a PCB layout
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Golden AI
edited on 23 Nov, 2021
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US Patent 7343582 Optical proximity correction using progressively smoothed mask shapes

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