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US Patent 11385278 Security circuitry for bonded structures
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Patent
Date Filed
May 22, 2020
Date of Patent
July 12, 2022
Patent Application Number
16881621
Patent Citations
US Patent 11205625 Wafer-level bonding of obstructive elements
US Patent 10923408 Cavity packages
US Patent 10002844 Bonded structures
US Patent 10014429 Semiconductor structures including bonding layers, multi-junction photovoltaic cells and related methods
US Patent 10026605 Method of reducing residual contamination in singulated semiconductor die
US Patent 10026716 3DIC formation with dies bonded to formed RDLs
US Patent 10075657 Edgeless large area camera system
US Patent 10204893 Stacked dies and methods for forming bonded structures
US Patent 10269708 Increased contact alignment tolerance for direct bonding
US Patent 10269756 Die processing
•••
Patent Citations Received
US Patent 12125784 Interconnect structures
0
US Patent 11694925 Diffusion barrier collar for interconnects
0
US Patent 11756880 Interconnect structures
US Patent 11790219 Three dimensional circuit implementing machine trained network
US Patent 11978724 Diffused bitline replacement in memory
0
US Patent 12068278 Processed stacked dies
0
US Patent 12074092 Hard IP blocks with physically bidirectional passageways
0
US Patent 12113054 Non-volatile dynamic random access memory
0
US Patent 12113056 Stacked dies and methods for forming bonded structures
0
US Patent 11621246 Diffused bitline replacement in stacked wafer memory
0
•••
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11385278
Patent Primary Examiner
Nathan W Ha
CPC Code
H01L 24/80
H01L 23/53238
H01L 23/5384
G01R 31/2853
G01R 31/70
H01L 24/10
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