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US Patent 11676821 Self-aligned double patterning

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
September 11, 2020
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Date of Patent
June 13, 2023
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Patent Application Number
17018705
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Patent Citations
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US Patent 8822243 Light emitting devices having light coupling layers with recessed electrodes
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US Patent 9053279 Pattern modification with a preferred position function
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US Patent 9093530 Fin structure of FinFET
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US Patent 9099530 Methods of patterning small via pitch dimensions
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US Patent 9153478 Spacer etching process for integrated circuit design
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US Patent 9455194 Method for fabricating semiconductor device
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US Patent 9501601 Layout optimization of a main pattern and a cut pattern
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US Patent 9548303 FinFET devices with unique fin shape and the fabrication thereof
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US Patent 10559492 Patterning methods for semiconductor devices and structures resulting therefrom
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US Patent 9748110 Method and system for selective spacer etch for multi-patterning schemes
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•••
Patent Citations Received
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US Patent 12068168 Processes for reducing line-end spacing
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US Patent 12068167 Self-aligned double patterning
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11676821
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Patent Primary Examiner
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Robert G Bachner
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CPC Code
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H01L 21/76802
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H01L 21/76898
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H01L 21/0337
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H01L 21/76811
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H01L 21/76816
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H01L 21/3085
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H01L 21/0338
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H01L 21/0332
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H01L 21/3081
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H01L 21/3086
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•••

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