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Hoai Pham

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Edits on 20 Aug, 2022
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godwinno feliks
edited on 20 Aug, 2022
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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Infobox (-134 properties)
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Patent primary examiner of
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US Patent 7091587 Semiconductor device
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US Patent 7094666 Method and system for fabricating strained layers for the manufacture of integrated circuits
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US Patent 7095090 Photoelectric conversion device
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US Patent 7098043 PCMO spin-coat deposition
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US Patent 7098531 Jumper chip component and mounting structure therefor
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US Patent 7098540 Electrical interconnect with minimal parasitic capacitance
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US Patent 7101732 Semiconductor device and method of manufacturing the same
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US Patent 7102187 Gate structure of a semiconductor device
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US Patent 7102208 Leadframe and semiconductor package with improved solder joint strength
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US Patent 7105416 Method for controlling the top width of a trench
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US Patent 7105881 DRAMS constructions and DRAM devices
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US Patent 7105882 Semiconductor device memory cell
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US Patent 7105892 Semiconductor device having a wave-like channel region
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US Patent 7105899 Transistor structure having reduced transistor leakage attributes
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US Patent 7109570 Integrated circuit package with leadframe enhancement and method of manufacturing the same
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US Patent 7112471 Leadless packaging for image sensor devices and methods of assembly
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US Patent 7112815 Multi-layer memory arrays
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US Patent 7112884 Integrated circuit having memory disposed thereon and method of making thereof
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US Patent 7115930 Semiconductor memory device including multi-layer gate structure
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US Patent 7115954 Semiconductor device including stress inducing films formed over n-channel and p-channel field effect transistors and a method of manufacturing the same
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US Patent 7115955 Semiconductor device having a strained raised source/drain
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US Patent 7119020 Method for fabricating semiconductor device
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US Patent 7119406 Semiconductor integrated circuit device having deposited layer for gate insulation
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US Patent 7119413 High-voltage transistor having shielding gate
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US Patent 7122412 Method of fabricating a necked FINFET device
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US Patent 7122415 Atomic layer deposition of interpoly oxides in a non-volatile memory device
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US Patent 7122851 Semiconductor device with perovskite capacitor
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US Patent 7126220 Miniaturized contact spring
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US Patent 7129058 Method of production of a nanoparticle of a compound semiconductor in a cavity of protein
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US Patent 7129537 Stacked gate flash memory device and method of fabricating the same
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US Patent 7132708 Semiconductor memory device having self-aligned contacts and method of fabricating the same
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US Patent 7132738 Semiconductor device having multiple semiconductor chips stacked in layers and method for manufacturing the same, circuit substrate and electronic apparatus
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US Patent 7135729 Semiconductor memory device including multi-layer gate structure
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US Patent 7137830 Miniaturized contact spring
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US Patent 7138312 Semiconductor device and method for fabricating the same
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US Patent 7138344 Method for minimizing slip line faults on a semiconductor wafer surface
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US Patent 7138655 Thin film transistor array panel including symmetrically aligned thin film transistors and manufacturing method thereof
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US Patent 7138675 Semiconductor devices having storage nodes
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US Patent 7141816 Field effect transistor
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US Patent 7141831 Snapback clamp having low triggering voltage for ESD protection
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US Patent 7141849 Semiconductor storage device having a function to convert changes of an electric charge amount to a current amount
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US Patent 7145248 Common connection method for flip-chip assembled devices
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US Patent 7148085 Gold spot plated leadframes for semiconductor devices and method of fabrication
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US Patent 7148096 Method of manufacturing a semiconductor device having a gate electrode containing polycrystalline silicon-germanium
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US Patent 7148552 High voltage transistor having side-wall width different from side-wall width of a low voltage transistor
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US Patent 7148563 Multi-chip package for reducing parasitic load of pin
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US Patent 7157305 Forming multi-layer memory arrays
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US Patent 7157324 Transistor structure having reduced transistor leakage attributes
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US Patent 7157330 Process for fabricating semiconductor device
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US Patent 7157365 Semiconductor device having a dummy conductive via and a method of manufacture therefor
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US Patent 7157752 Semiconductor device
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US Patent 7157776 Semiconductor device, manufacturing method thereof, and CMOS integrated circuit device
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US Patent 7160770 Method of manufacturing an electronic component including an inter-line insulating layer and a conductor pattern
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US Patent 7160785 Container capacitor structure and method of formation thereof
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US Patent 7163859 Method of manufacturing capacitors for semiconductor devices
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US Patent 7164173 Method for manufacturing MOS transistor and semiconductor device employing MOS transistor made using the same
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US Patent 7166495 Method of fabricating a multi-die semiconductor package assembly
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US Patent 7170107 IC chip having a protective structure
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US Patent 7172934 Method of manufacturing a semiconductor device with a silicon-germanium gate electrode
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US Patent 7179686 Manufacturing method of semiconductor device
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US Patent 7180106 Semiconductor device having enhanced di/dt tolerance and dV/dt tolerance
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US Patent 7180164 Semiconductor device
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US Patent 7187054 Diode and method for manufacturing the same
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US Patent 7187060 Semiconductor device with shield
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US Patent 7189616 Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same
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US Patent 7195954 Low capacitance coupling wire bonded semiconductor device
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US Patent 7195964 Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit
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US Patent 7195971 Method of manufacturing an intralevel decoupling capacitor
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US Patent 7196358 Light emitting diode module with high heat dissipation
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US Patent 7196381 Corner protection to reduce wrap around
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US Patent 7199000 Method for manufacturing semiconductor device
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US Patent 7199014 Field effect transistor and method of manufacturing the same
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US Patent 7199414 Stress-reduced layer system for use in storage capacitors
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US Patent 7199430 Advanced CMOS using super steep retrograde wells
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US Patent 7199468 Hybrid integrated circuit device with high melting point brazing material
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US Patent 7205224 Very low dielectric constant plasma-enhanced CVD films
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US Patent 7205570 Thin film transistor array panel
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US Patent 7208353 Semiconductor device and manufacturing method thereof
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US Patent 7208365 Nonvolatile memory device and method of manufacturing the same
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US Patent 7208758 Dynamic integrated circuit clusters, modules including same and methods of fabricating
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US Patent 7208776 Fuse corner pad for an integrated circuit
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US Patent 7211477 High voltage field effect device and method
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US Patent 7211846 Transistor having compensation zones enabling a low on-resistance and a high reverse voltage
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US Patent 7211867 Thin film memory, array, and operation method and manufacture method therefor
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US Patent 7211884 Implantable medical device construction using a flexible substrate
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US Patent 7211885 Vertical electrical interconnections in a stack
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US Patent 7214970 Hermetic container and image display apparatus
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US Patent 7217973 Semiconductor device including sidewall floating gates
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US Patent 7221054 Bump structure
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US Patent 7224022 Vertical type semiconductor device and method of manufacturing the same
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US Patent 7224076 Electronic component package
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US Patent 7227230 Low-K gate spacers by fluorine implantation
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US Patent 7230283 Semiconductor device having a metal conductor in ohmic contact with the gate region on the bottom of each groove
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US Patent 7239026 Semiconductor device having die attachment and die pad for applying tensile or compressive stress to the IC chip
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US Patent 7241653 Nonplanar device with stress incorporation layer and method of fabrication
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US Patent 7241656 Semiconductor device and its manufacture method, and measurement fixture for the semiconductor device
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US Patent 7242430 High dynamic range image sensor cell
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US Patent 7247904 Semiconductor device memory cell
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US Patent 7247913 Semiconductor device having a Schottky source/drain transistor
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US Patent 7250655 MOS transistor having a T-shaped gate electrode
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US Patent 7256105 Semiconductor substrate and thin processing method for semiconductor substrate
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US Patent 7256119 Semiconductor device having trench structures and method
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US Patent 7256474 Semiconductor device having a guard ring
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US Patent 7256485 Semiconductor device having bonding pad of the first chip thicker than bonding pad of the second chip
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US Patent 7256500 Semiconductor device using metal nitride as insulating film
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US Patent 7262512 Surface mount chip package
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US Patent 7268039 Method of forming a contact using a sacrificial structure
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US Patent 7268401 Semiconductor integrated circuit device having deposited layer for gate insulation
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US Patent 7268439 Semiconductor device having resin-sealed area on circuit board thereof
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US Patent 7271449 Semiconductor device having triple-well structure
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US Patent 7273779 Method of forming a double-sided capacitor
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US Patent 7274083 Semiconductor device with surge current protection and method of making the same
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US Patent 7274086 Memory device power distribution in memory assemblies
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US Patent 7276771 Diode and method for manufacturing the same
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US Patent 7276785 Electronic module, panel having electronic modules which are to be divided up, and process for the production thereof
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US Patent 7279796 Microelectronic die having a thermoelectric module
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US Patent 7282407 Semiconductor memory device and method of manufacturing for preventing bit line oxidation
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US Patent 7282756 Structurally-stabilized capacitors and method of making of same
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US Patent 7285462 Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same
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US Patent 7285838 Semiconductor device and method of manufacturing the same
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US Patent 7288790 Thin film transistor array panel and manufacturing method thereof
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US Patent 7288795 Semiconductor light-emitting device and method for manufacturing the device
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US Patent 7288820 Low voltage NMOS-based electrostatic discharge clamp
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US Patent 7291879 Semiconductor memory device including capacitor with conductive hydrogen diffusion prevention wiring film
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US Patent 7297596 Method of manufacturing a semiconductor device having a switching function
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US Patent 7297984 Semiconductor light-emitting device and method for manufacturing the device
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US Patent 7297999 Semiconductor device with capacitors and its manufacture method
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US Patent 7301187 High voltage field effect device and method
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US Patent 7302671 Integrated circuit logic with self compensating shapes
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US Patent 7304389 Semiconductor device and supporting plate
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US Patent 7312516 Chip scale package with heat spreader
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US Patent 7315045 Sapphire/gallium nitride laminate having reduced bending deformation
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US Patent 7315046 Semiconductor light-emitting device and method for manufacturing the device
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US Patent 7344940 Methods of fabricating integrated circuit ferroelectric memory devices including plate lines directly on ferroelectric capacitors
Edits on 24 Nov, 2021
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Golden AI
edited on 24 Nov, 2021
Edits on 23 Nov, 2021
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7315046 Semiconductor light-emitting device and method for manufacturing the device
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7315045 Sapphire/gallium nitride laminate having reduced bending deformation
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7312516 Chip scale package with heat spreader
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7304389 Semiconductor device and supporting plate
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7302671 Integrated circuit logic with self compensating shapes
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7301187 High voltage field effect device and method
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7297999 Semiconductor device with capacitors and its manufacture method
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7297984 Semiconductor light-emitting device and method for manufacturing the device
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7297596 Method of manufacturing a semiconductor device having a switching function
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7288820 Low voltage NMOS-based electrostatic discharge clamp
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7288790 Thin film transistor array panel and manufacturing method thereof
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7288795 Semiconductor light-emitting device and method for manufacturing the device
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7285838 Semiconductor device and method of manufacturing the same
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Golden AI
edited on 23 Nov, 2021
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7282756 Structurally-stabilized capacitors and method of making of same
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Golden AI
edited on 23 Nov, 2021

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