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US Patent 11670601 Stacking via structures for stress reduction
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Patent
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Date Filed
December 18, 2020
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Date of Patent
June 6, 2023
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Patent Application Number
17126957
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Patent Citations
US Patent 8778738 Packaged semiconductor devices and packaging devices and methods
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US Patent 8829676 Interconnect structure for wafer level package
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US Patent 9000584 Packaged semiconductor device with a molding compound and a method of forming the same
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US Patent 9048222 Method of fabricating interconnect structure for package-on-package devices
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US Patent 9048233 Package systems having interposers
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US Patent 9064879 Packaging methods and structures using a die attach film
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US Patent 9111949 Methods and apparatus of wafer level package for heterogeneous integration technology
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US Patent 9263511 Package with metal-insulator-metal capacitor and method of manufacturing the same
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US Patent 9281254 Methods of forming integrated circuit package
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US Patent 9372206 Testing of semiconductor chips with microbumps
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•••
Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11670601
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Patent Primary Examiner
Selim U Ahmed
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CPC Code
H01L 21/76895
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H01L 2224/8385
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H01L 23/562
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H01L 21/4853
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H01L 21/4857
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H01L 21/563
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H01L 23/3185
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H01L 23/5383
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H01L 23/5386
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H01L 24/16
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•••
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