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US Patent 11854921 Integrated circuit package and method

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
July 25, 2022
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Date of Patent
December 26, 2023
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Patent Application Number
17872916
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Patent Citations
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US Patent 9281254 Methods of forming integrated circuit package
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US Patent 9299649 3D packages and methods for forming the same
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US Patent 9372206 Testing of semiconductor chips with microbumps
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US Patent 9425126 Dummy structure for chip-on-wafer-on-substrate
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US Patent 9443783 3DIC stacking device and method of manufacture
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US Patent 9461018 Fan-out PoP structure with inconsecutive polymer layer
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US Patent 9496189 Stacked semiconductor devices and methods of forming same
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US Patent 9666502 Discrete polymer in fan-out packages
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US Patent 9735134 Packages with through-vias having tapered ends
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US Patent 9735131 Multi-stack package-on-package structures
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•••
Patent Inventor Names
Sung-Feng Yeh
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Hsien-Wei Chen
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Tzuan-Horng Liu
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Chen-Hua Yu
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Ming-Fa Chen
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11854921
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Patent Primary Examiner
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Theresa T Doan
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CPC Code
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H01L 23/5383
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H01L 23/5389
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H01L 24/80
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H01L 25/105
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H01L 2224/08145
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H01L 2224/32225
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H01L 2224/94
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H01L 2224/97
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H01L 2924/15311
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H01L 2221/68345
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•••

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