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Golden has been acquired by ComplyAdvantage.
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Linh My Nguyen
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Edits on 20 Aug, 2022
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godwinno feliks
edited on 20 Aug, 2022
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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
US Patent 7088168 Direct conversion receiver using vertical bipolar junction transistor available in deep n-well CMOS technology
US Patent 7095264 Programmable jitter signal generator
US Patent 7098706 High speed synchronizer for simultaneously initializing rising edge triggered and falling edge triggered flip-flops
US Patent 7098707 Highly configurable PLL architecture for programmable logic
US Patent 7098713 Delay circuit having function of filter circuit
US Patent 7098714 Centralizing the lock point of a synchronous circuit
US Patent 7102398 Circuit for two PLLs for horizontal deflection
US Patent 7102400 Phase locked loop charge pump and method of operation
US Patent 7106112 Apparatus for generating power-up signal
US Patent 7106114 Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero
US Patent 7109767 Generating different delay ratios for a strobe delay
US Patent 7109769 PWM signal generator
US Patent 7109773 Flexible blender
US Patent 7113010 Clock distortion detector using a synchronous mirror delay circuit
US Patent 7113011 Low power PLL for PWM switching digital control power supply
US Patent 7113012 Skew delay compensator
US Patent 7113014 Pulse width modulator
US Patent 7113015 Circuit for setting a signal propagation time for a signal on a signal line and method for ascertaining timing parameters
US Patent 7116141 Frequency-doubling delay locked loop
US Patent 7116142 Apparatus and method for accurately tuning the speed of an integrated circuit
US Patent 7116145 Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof
US Patent 7119582 Phase detection in a sync pulse generator
US Patent 7119589 Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof
US Patent 7119592 Delay locked loop circuit with time delay quantifier and control
US Patent 7123064 Digital phase shift circuits
US Patent 7123069 Latch or phase detector device
US Patent 7123077 Four-phase charge pump circuit with reduced body effect
US Patent 7126385 Differential inverter circuit
US Patent 7126388 Power MOSFET driver and method therefor
US Patent 7126392 Semiconductor integrated device having reduced jitter and reduced current consumption
US Patent 7126399 Memory interface phase-shift circuitry to support multiple frequency ranges
US Patent 7126400 Delay adjustment circuit, integrated circuit device, and delay adjustment method
US Patent 7126401 Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device
US Patent 7129757 Clock frequency detect with programmable jitter tolerance
US Patent 7129760 Timing vernier using a delay locked loop
US Patent 7132869 Zero idle time Z-state circuit for phase-locked loops, delay-locked loops, and switching regulators
US Patent 7132872 Apparatus and method for generating a phase delay
US Patent 7135897 Clock resynchronizer
US Patent 7135900 Phase locked loop with adaptive loop bandwidth
US Patent 7135905 High speed clock and data recovery system
US Patent 7138837 Digital phase locked loop circuitry and methods
US Patent 7138841 Programmable phase shift and duty cycle correction circuit and method
US Patent 7142024 Power on reset circuit
US Patent 7142042 Nulled error amplifier
US Patent 7148728 Digital delay device, digital oscillator clock signal generator and memory interface
US Patent 7148729 Delay locked loop using synchronous mirror delay
US Patent 7148730 Z-state circuit for phase-locked loops
US Patent 7148731 Duty cycle correction
US Patent 7148732 Semiconductor integrated circuit
US Patent 7151396 Clock delay compensation circuit
US Patent 7151398 Clock signal generators having programmable full-period clock skew control
US Patent 7154311 Delay locked loop in semiconductor memory device and locking method thereof
US Patent 7161391 Skew tolerant high-speed digital phase detector
US Patent 7161392 Comparator feedback peak detector
US Patent 7161397 Digital delay locked loop capable of correcting duty cycle and its method
US Patent 7161398 VCDL-based dual loop DLL having infinite phase shift function
US Patent 7161412 Analog calibration of a current source array at low supply voltages
US Patent 7164303 Delay circuit, ferroelectric memory device and electronic equipment
US Patent 7164310 Systems and apparatus for digital control of bias for transistors
US Patent 7170322 System and method for reducing transient response in a fractional N phase lock loop
US Patent 7170326 Pulse-on-edge circuit
US Patent 7170332 Reference signal generators
US Patent 7173459 Trimming method and apparatus for voltage controlled delay loop with central interpolator
US Patent 7173460 Sampling phase detector for delay-locked loop
US Patent 7173480 Device for controlling the operation of internal voltage generator
US Patent 7176726 Integrated loss of signal detection with wide threshold range and precise hysteresis
US Patent 7176732 Device and method for increasing the operating range of an electrical circuit
US Patent 7176733 High output impedance charge pump for PLL/DLL
US Patent 7176740 Level conversion circuit
US Patent 7176747 Multi-level high voltage generator
US Patent 7180343 Apparatus for synchronizing clock using source synchronous clock in optical transmission system
US Patent 7183819 Method and circuit configuration for synchronous resetting of a multiple clock domain circuit
US Patent 7183821 Apparatus and method of controlling clock phase alignment with dual loop of hybrid phase and time domain for clock source synchronization
US Patent 7183823 Method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, and a switch mode power converter
US Patent 7183824 Duty cycle correction circuit and a method for duty cycle correction in a delay locked loop using an inversion locking scheme
US Patent 7183830 Integrated circuit and method for generating a clock signal
US Patent 7187217 Clock frequency divider and trigger signal generation circuit for same
US Patent 7190196 Dual-edge synchronized data sampler
US Patent 7190198 Voltage controlled delay loop with central interpolator
US Patent 7196561 Programmable reset signal that is independent of supply voltage ramp rate
US Patent 7199623 Method and apparatus for providing a power-on reset signal
US Patent 7199624 Phase locked loop system capable of deskewing
US Patent 7199625 Delay locked loop structure providing first and second locked clock signals
US Patent 7199632 Duty cycle correction circuit for use in a semiconductor device
US Patent 7199644 Bias circuit having transistors that selectively provide current that controls generation of bias voltage
US Patent 7202709 Waveform output device and drive device
US Patent 7202714 Amplifier circuit with output delay selectively changed according to common mode voltage level, associated replica delay circuit and internal clock generator
US Patent 7202715 Matched current delay cell and delay locked loop
US Patent 7202716 Apparatus and method of controlling and tuning a fine calibration for clock source synchronization in dual loop of hybrid phase and time domain
US Patent 7205802 Apparatus and method for controlling a delay chain
US Patent 7205805 Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error
US Patent 7205810 Skew tolerant phase shift driver with controlled reset pulse width
US Patent 7205813 Differential type delay cells and methods of operating the same
US Patent 7205815 Method and integrated circuit apparatus for reducing simultaneously switching output
US Patent 7205819 Zero-bias-power level shifting
US Patent 7205828 Voltage regulator having a compensated load conductance
US Patent 7208986 Measure-controlled delay circuits with reduced phase error
US Patent 7208988 Clock generator
US Patent 7208995 Charge pump circuit and amplifier
US Patent 7212047 Semiconductor integrated circuit having built-in PLL circuit
US Patent 7212049 Digital-control-type phase-composing circuit system
US Patent 7215164 Capacitance multiplier with enhanced gain and low power consumption
US Patent 7215165 Clock generating circuit and clock generating method
US Patent 7218164 Emitter switching driving network to control the storage time
US Patent 7221196 Low-power low-voltage multi-level variable-resistor line driver
US Patent 7221203 Pulse-width modulator circuit and method for controlling a pulse width modulator circuit
US Patent 7224198 Input and output circuit and method of operation thereof
US Patent 7227393 Method and apparatus for adaptive delay cancellation in high-speed wireline transmitters
US Patent 7230467 Constant edge generation circuits and methods and systems using the same
US Patent 7230475 Semiconductor devices including an external power voltage control function and methods of operating the same
US Patent 7230495 Phase-locked loop circuits with reduced lock time
US Patent 7233179 Output stage interface circuit for outputting digital data onto a data bus
US Patent 7233182 Circuitry for eliminating false lock in delay-locked loops
US Patent 7233186 Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit
US Patent 7236024 Configurable circuit structure having reduced susceptibility to interference when using at least two such circuits to perform like functions
US Patent 7236025 PLL circuit and program for same
US Patent 7236026 Circuit for and method of generating a frequency aligned clock signal
US Patent 7236027 Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof
US Patent 7236033 System and method for detecting processing speed of integrated circuit
US Patent 7239185 Driver circuit connected to pulse shaping circuitry
US Patent 7239189 Clock generating circuit
US Patent 7242228 Method and device for generating an output signal having a predetermined phase shift with respect to an input signal
US Patent 7242231 Programmable fractional-N clock generators
US Patent 7242239 Programming and determining state of electrical fuse using field effect transistor having multiple conduction states
US Patent 7248086 Leakage compensation for capacitors in loop filters
US Patent 7253668 Delay-locked loop with feedback compensation
US Patent 7253672 System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
US Patent 7256631 Charge pump with balanced and constant up and down currents
US Patent 7259596 Circuit arrangement for monitoring a voltage
US Patent 7259598 Clock switching circuit
US Patent 7259608 System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
US Patent 7262642 Semiconductor integrated circuit comprising first and second transmission systems
US Patent 7265590 Semiconductor apparatus for monitoring critical path delay characteristics of a target circuit
US Patent 7271628 Reduced current input buffer circuit
US Patent 7271633 Charge pump structure for reducing capacitance in loop filter of a phase locked loop
US Patent 7271634 Delay-locked loop having a plurality of lock modes
US Patent 7271644 Multi-state electrical fuse
US Patent 7274228 Method and apparatus for digital phase generation at high frequencies
US Patent 7274236 Variable delay line with multiple hierarchy
US Patent 7276941 Power up circuit of semiconductor memory device and compensating method thereof
US Patent 7276943 Highly configurable PLL architecture for programmable logic
US Patent 7276944 Clock generation circuit and clock generation method
US Patent 7276945 Low power and low timing jitter phase-lock loop and method
US Patent 7276960 Voltage regulated charge pump with regulated charge current into the flying capacitor
US Patent 7282963 Wide-band circuit coupled through a transmission line
US Patent 7282969 Low divide ratio programmable frequency divider and method thereof
US Patent 7282976 Apparatus and method for duty cycle correction
US Patent 7282977 Duty cycle correction device
US Patent 7282978 Duty cycle correction device
US Patent 7285994 Rotational frequency detector system
US Patent 7289592 Apparatus for multiple-divisor prescaler
US Patent 7292070 Programmable PPM detector
US Patent 7292077 Phase-lock loop and loop filter thereof
US Patent 7292079 DLL-based programmable clock generator using a threshold-trigger delay element circuit and a circular edge combiner
US Patent 7292081 Pulse generator
US Patent 7292085 Timing delay generator and method using temperature stabilisation
US Patent 7292086 Delay circuit and semiconductor device
US Patent 7295047 Output buffer with improved slew rate and method thereof
US Patent 7295049 Method and circuit for rapid alignment of signals
US Patent 7295053 Delay-locked loop circuits
US Patent 7298180 Latch type sense amplifier
US Patent 7298183 High frequency divider circuits and methods
US Patent 7298184 Frequency divider circuit with controllable frequency division ratio and method for frequency division in a frequency divider circuit
US Patent 7298188 Timing adjustment circuit and memory controller
US Patent 7298191 Reset-free delay-locked loop
US Patent 7298193 Methods and arrangements to adjust a duty cycle
US Patent 7301373 Asymmetric precharged flip flop
US Patent 7304513 Area efficient programmable frequency divider
US Patent 7304524 Data interface circuit and data transmitting method
US Patent 7307459 Programmable phase-locked loop circuitry for programmable logic device
US Patent 7307464 System and method for switching between high voltage and low voltage
US Patent 7307467 Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices
US Patent 7310010 Duty cycle corrector
US Patent 7317343 Pulse-generation circuit with multi-delay block and set-reset latches
US Patent 7319348 Circuits for locally generating non-integral divided clocks with centralized state machines
US Patent 7319354 Signal processing apparatus having internal clock signal source
US Patent 7321244 Clock switching device and clock switching method
US Patent 7321248 Phase adjustment method and circuit for DLL-based serial data link transceivers
US Patent 7321250 Integrated circuit device
US Patent 7323915 Delay locked loop with selectable delay
US Patent 7323924 Level shifter circuit
US Patent 7327172 Integrated clock generator with programmable spread spectrum using standard PLL circuitry
US Patent 7327174 Fast locking mechanism for delay lock loops and phase lock loops
US Patent 7332948 Duty cycle correction circuit of a DLL circuit
US Patent 7342428 Pulse-on-edge circuit
US Patent RE40168 Low power circuit with proper slew rate by automatic adjustment of bias current
US Patent 7362152 Apparatus and method for digital phase control of a pulse width modulation generator for microprocessor/DSP in integrated circuits
US Patent 7439788 Receive clock deskewing method, apparatus, and system
Edits on 1 Dec, 2021
Golden AI
edited on 1 Dec, 2021
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Patent primary examiner of
US Patent 7439788 Receive clock deskewing method, apparatus, and system
Edits on 25 Nov, 2021
Golden AI
edited on 25 Nov, 2021
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Patent primary examiner of
US Patent 7362152 Apparatus and method for digital phase control of a pulse width modulation generator for microprocessor/DSP in integrated circuits
Edits on 24 Nov, 2021
Golden AI
edited on 24 Nov, 2021
Edits made to:
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Patent primary examiner of
US Patent RE40168 Low power circuit with proper slew rate by automatic adjustment of bias current
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7342428 Pulse-on-edge circuit
Edits on 23 Nov, 2021
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7332948 Duty cycle correction circuit of a DLL circuit
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7327174 Fast locking mechanism for delay lock loops and phase lock loops
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7327172 Integrated clock generator with programmable spread spectrum using standard PLL circuitry
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7323924 Level shifter circuit
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7323915 Delay locked loop with selectable delay
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7321248 Phase adjustment method and circuit for DLL-based serial data link transceivers
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7321244 Clock switching device and clock switching method
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7321250 Integrated circuit device
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7319354 Signal processing apparatus having internal clock signal source
Golden AI
edited on 23 Nov, 2021
Edits made to:
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Patent primary examiner of
US Patent 7319348 Circuits for locally generating non-integral divided clocks with centralized state machines
Golden AI
edited on 23 Nov, 2021
Edits made to:
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+1
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Patent primary examiner of
US Patent 7317343 Pulse-generation circuit with multi-delay block and set-reset latches
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7310010 Duty cycle corrector
Golden AI
edited on 23 Nov, 2021
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Patent primary examiner of
US Patent 7307467 Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices
Golden AI
edited on 23 Nov, 2021
Edits made to:
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Patent primary examiner of
US Patent 7307464 System and method for switching between high voltage and low voltage
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