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US Patent 12073082 High capacity memory circuit with low effective latency

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 US Patent 12073082 High capacity memory circuit with low effective latency

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Patent abstract

A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
120730820
Patent Inventor Names
Eli Harari0
Khandker Nazrul Quader0
Richard S. Chernicoff0
Robert D. Norman0
Sayeef Salahuddin0
Tianhong Yan0
Youn Cheul Kim0
Date of Patent
August 27, 2024
0
Patent Application Number
183060730
Date Filed
April 24, 2023
0
Patent Citations
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Patent Primary Examiner
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Pho M Luu
0
CPC Code
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G06F 3/0631
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G06F 3/0611
0

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