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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7088633 Method and system for providing seamless self-refresh for directed bank refresh in volatile memories
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US Patent 7099174 Metal wiring pattern for memory devices
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US Patent 7099176 Non-orthogonal write line structure in MRAM
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US Patent 7099190 Data storage system
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US Patent 7099199 Nonvolatile semiconductor memory device
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US Patent 7105879 Write line design in MRAM
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US Patent 7106626 Serially sensing the output of multilevel cell arrays
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US Patent 7110285 Magnetic memory device
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US Patent 7110286 Phase-change memory device and method of writing a phase-change memory device
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US Patent 7113415 Match line pre-charging in a content addressable memory having configurable rows
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US Patent 7113434 Semiconductor integrated circuit having programmable delays for generating timing signals with time difference being non-integral multiple of clock cycle
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US Patent 7120041 Memory device with programmable parameter controller
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US Patent 7120060 Memory device with non-volatile reference memory cell trimming capabilities
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US Patent 7120082 System for reducing row periphery power consumption in memory devices
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US Patent 7123539 Memory modules with magnetoresistive elements and method of reading data from row or column directions
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US Patent 7130211 Interleave control device using nonvolatile ferroelectric memory
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US Patent 7130237 Control circuit for stable exit from power-down mode
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US Patent 7133310 Thin film magnetic memory device having a highly integrated memory array
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US Patent 7136309 FIFO with multiple data inputs and method thereof
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US Patent 7136312 Semiconductor device having read and write operations corresponding to read and write row control signals
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US Patent 7154809 Method for measuring the delay time of a signal line
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US Patent 7158438 Network packet buffer allocation optimization in memory bank systems
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US Patent 7158440 FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation
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US Patent 7161821 Apparatus and method for mounting microelectronic devices on a mirrored board assembly
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US Patent 7161854 Jitter and skew suppressing delay control apparatus
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US Patent 7170775 MRAM cell with reduced write current
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US Patent 7173869 Regulating voltages in semiconductor devices
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US Patent 7173876 Semiconductor integrated circuit
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US Patent 7177181 Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics
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US Patent 7184300 Magneto resistance random access memory element
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US Patent 7184336 Method and test structure for evaluating threshold voltage distribution in a memory array
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US Patent 7187612 Memory having power-up circuit
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US Patent 7193902 Method of erasing a flash memory cell
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US Patent 7196941 Semiconductor memory device and method for writing and reading data
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US Patent 7196957 Magnetic memory structure using heater lines to assist in writing operations
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US Patent 7203111 Method and apparatus for driver circuit in a MEMS device
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US Patent 7206233 Memory system with parallel data transfer between host, buffer and flash memory
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US Patent 7206243 Method of rewriting a logic state of a memory cell
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US Patent 7215590 Semiconductor die with process variation compensated operating voltage
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US Patent 7221588 Memory array incorporating memory cells arranged in NAND strings
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US Patent 7221606 Semiconductor memory device for low power system comprising sense amplifier with operating voltages lower/higher than ground/voltage supply and auxiliary sense amplifier
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US Patent 7221607 Multi-port memory systems and methods for bit line coupling
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US Patent 7221610 Charge pump circuit for generating high voltages required in read/write/erase/standby modes in non-volatile memory device
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US Patent 7224602 Semiconductor memory device and control method having data protection feature
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US Patent 7224604 Method of achieving wear leveling in flash memory using relative grades
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US Patent 7224611 Virtual ground line type memory device with high speed readout circuit
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US Patent 7224629 Memory device having high speed sense amplifier comprising pull-up circuit and pull-down circuits with different drivability for each
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US Patent 7224630 Antifuse circuit
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US Patent 7236412 Integrated semiconductor memory with redundant memory cells replaceable for either true or complementary defective memory cells
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US Patent 7239566 Semiconductor memory device and method of precharging global input/output lines thereof
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US Patent 7245525 Data restore in thryistor based memory devices
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US Patent 7245538 High voltage generation and regulation circuit in a memory device
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US Patent 7248518 Self-timed memory device providing adequate charging time for selected heaviest loading row
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US Patent 7248524 Operating temperature optimization in a ferroelectric or electret memory
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US Patent 7251158 Erase algorithm for multi-level bit flash memory
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US Patent 7254058 Thin film magnetic memory device provided with program element
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US Patent 7254085 Static random access memory device and method of reducing standby current
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US Patent 7254089 Memory with selectable single cell or twin cell configuration
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US Patent 7257012 Nonvolatile semiconductor memory device using irreversible storage elements
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US Patent 7263003 Two-transistor flash memory device using replica cell array to control the precharge/discharge and sense amplifier circuits of the primary cell array
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US Patent 7263007 Semiconductor memory device using read data bus for writing data during high-speed writing
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US Patent 7266006 Multiple-layer serial diode cell and nonvolatile memory device using the same
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US Patent 7274597 Method of programming of a non-volatile memory cell comprising steps of applying constant voltage and then constant current
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US Patent 7280387 SRAM cell comprising a reference transistor for neutralizing leakage current and associated read and write method
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US Patent 7283408 Nonvolatile memory apparatus enabling data to be replaced prior to supplying read data and prior to supplying write data
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US Patent 7286436 High-density memory module utilizing low-density memory components
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US Patent 7289359 Systems and methods for using a single reference cell in a dual bit flash memory
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US Patent 7289368 Control of voltages during erase and re-program operations of memory cells
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US Patent 7289376 Method for eliminating crosstalk in a metal programmable read only memory
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US Patent 7292491 Method and apparatus for controlling refresh operations in a dynamic memory device
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US Patent 7295455 Semiconductor integrated circuit with photo-detecting elements for reverse-engineering protection
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US Patent 7298638 Operating an electronic device having a vertical gain cell that includes vertical MOS transistors
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US Patent 7298639 Reprogrammable electrical fuse
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US Patent 7298663 Bit line control for low power in standby
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US Patent 7301815 Semiconductor memory device comprising controllable threshould voltage dummy memory cells
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US Patent 7301849 System for reducing row periphery power consumption in memory devices
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US Patent 7304889 Serially sensing the output of multilevel cell arrays
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US Patent 7304901 Enabling memory redundancy during testing
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US Patent 7304907 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
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US Patent 7313042 Thin film magnetic memory device having an improved read operation margin
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US Patent 7319609 Non-volatile memory device with a programming current control scheme
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US Patent 7319629 Method of operating a dynamic random access memory cell
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US Patent 7321502 Non volatile data storage through dielectric breakdown
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US Patent 7327603 Memory device including electrical circuit configured to provide reversible bias across the PMC memory cell to perform erase and write functions
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US Patent 7327614 Memory device with programmable parameter controller
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US Patent 7330379 Semiconductor memory device having forced fail function of forcing a memory cell at a specific address to fail and method for testing same
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US Patent 7333379 Balanced sense amplifier circuits with adjustable transistor body bias
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US Patent 7339817 Thermally-assisted switching of magnetic memory elements
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US Patent 7339821 Dual-gate nonvolatile memory and method of program inhibition
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US Patent 7342830 Program and program verify operations for flash memory
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US Patent 7345939 Sense amplifiers having MOS transistors therein with different threshold voltages and/or that support different threshold voltage biasing
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US Patent 7345942 Memory circuit with automatic refresh function
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US Patent 7349247 Multi-layer magnetic switching element comprising a magnetic semiconductor layer having magnetization induced by applied voltage
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US Patent 7349280 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function
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US Patent 7352606 Monotonic counter using memory cells
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US Patent 7355875 Nonvolatile semiconductor memory device having capacitor arranged between power supplies to prevent voltage fluctuation
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US Patent 7355885 Semiconductor memory device with magnetoresistance elements and method of writing date into the same
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US Patent 7355887 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control
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US Patent 7355901 Synchronous output buffer, synchronous memory device and method of testing access time
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US Patent 7359259 Method for transmission and reception of a data signal on a line pair, as well as a transmission and reception circuit for this purpose
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US Patent 7359279 Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
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US Patent 7362629 Redundant circuit for semiconductor memory device
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US Patent 7362637 Current switching sensor detector
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US Patent 7362638 Semiconductor memory device for sensing voltages of bit lines in high speed
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US Patent 7372739 High voltage generation and regulation circuit in a memory device
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US Patent 7372741 Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile memory having circuitry which performs an erase operation and an erase verify operation when the processor specifies the erase operation mode to the nonvolatile memory
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US Patent 7376026 Integrated semiconductor memory having sense amplifiers selectively activated at different timing
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US Patent 7379342 Flash memory device being programmed and verified using voltage higher than target/read threshold voltage to achieve uniform threshold voltage characteristic
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US Patent 7379376 Internal address generator
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US Patent 7379383 Methods of DDR receiver read re-synchronization
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US Patent 7382642 Method and device for preventing erroneous programming of a magnetoresistive memory element
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US Patent 7382657 Semiconductor memory device having bit line precharge circuit controlled by address decoded signals
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US Patent 7385834 Data line layout in semiconductor memory device and method of forming the same
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US Patent 7388804 Semiconductor memory device for driving a word line
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US Patent 7391660 Address path circuit with row redundant scheme
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US Patent 7391663 Structure and method for measuring the channel boosting voltage of NAND flash memory at a node between drain/source select transistor and adjacent flash memory cell
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US Patent 7394719 Flash memory device with burst read mode of operation
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US Patent 7403420 Flash memory device and associated recharge method
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US Patent 7426128 Switchable resistive memory with opposite polarity write pulses
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US Patent 7426144 Semiconductor storage device
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US Patent 7433220 Two variable resistance elements being formed into a laminated layer with a common electrode and method of driving the same
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US Patent 7433245 Memory card able to guarantee a recoding rate and memory card system using the memory card
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US Patent 7436688 Priority encoder circuit and method
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US Patent 7436690 Flat cell read only memory using common contacts for bit lines and virtual ground lines
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US Patent 7436700 MRAM memory cell having a weak intrinsic anisotropic storage layer and method of producing the same
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US Patent 7436701 Single poly EPROM device with double control gates to prevent unintentionally charging/discharging
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US Patent 7436707 Flash memory cell structure and operating method thereof
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US Patent 7436718 Semiconductor memory device including fuse detection circuit to determine successful fuse-cutting rate for optical fuse-cutting conditions
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US Patent 7436729 Fuse circuit and semiconductor device using fuse circuit thereof
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US Patent 7440305 Semiconductor storage device with bit line structure disconnected in the middle of the array for reducing power consumption
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US Patent 7440348 Memory array having a redundant memory element
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US Patent 7443710 Control of memory devices possessing variable resistance characteristics
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US Patent 7443719 Superconducting circuit for high-speed lookup table
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US Patent 7447058 Write margin of SRAM cells improved by controlling power supply voltages to the inverters via corresponding bit lines
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US Patent 7450418 Non-volatile memory and operating method thereof
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US Patent 7450457 Memory system comprising a controller managing independent data transfer between input-output terminal, synchronous dynamic random access memory, and flash memory
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US Patent 7453716 Semiconductor memory device with stacked control transistors
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US Patent 7453723 Memory with weighted multi-page read
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US Patent 7453728 Data storage system with enhanced reliability with respect to data destruction caused by reading-out of the data
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US Patent 7453741 Semiconductor device card providing multiple working voltages
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US Patent 7457151 Phase change random access memory (PRAM) device having variable drive voltages
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US Patent 7457174 Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted
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US Patent 7457180 Method and apparatus for storing data in a write-once non-volatile memory
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US Patent 7463502 Ultra low-cost solid-state memory
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US Patent 7463538 Semiconductor memory device having a precharge control circuit for reducing current during continuous write operation
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US Patent 7466606 Memory device having terminals for transferring multiple types of data
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US Patent 7466620 System and method for low power wordline logic for a memory
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US Patent 7468924 Non-volatile memory device capable of reducing threshold voltage distribution
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US Patent 7471538 Memory module, system and method of making same
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US Patent 7471553 Phase change memory device and program method thereof
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US Patent 7471554 Phase change memory latch
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US Patent 7474549 Bit-line equalizer, semiconductor memory device including the same, and method for manufacturing bit-line equalizer
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US Patent 7474575 Apparatus for testing a memory of an integrated circuit
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US Patent 7477544 Storage device
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US Patent 7477555 System and method for differential eFUSE sensing without reference fuses
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US Patent 7480182 NOR flash memory devices in which a program verify operation is performed on selected memory cells and program verify methods associated therewith
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US Patent 7483289 Synchronous SRAM capable of faster read-modify-write operation
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US Patent 7486534 Diode-less array for one-time programmable memory
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US Patent 7486573 Flash memory device and voltage generating circuit for the same
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US Patent 7486588 Method and apparatus for driver circuit to provide a desired voltage level to a device
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US Patent 7489585 Global signal driver for individually adjusting driving strength of each memory bank
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US Patent 7492015 Complementary carbon nanotube triple gate technology
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US Patent 7492655 Memory device having high speed sense amplifier comprising pull-up circuit and pull-down circuits with drivability for each
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US Patent 7495985 Method and system for memory thermal load sharing using memory on die termination
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US Patent 7495987 Current-mode memory cell
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US Patent 7499331 Semiconductor memory device
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US Patent 7499344 Integrated circuit memory having a read circuit
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US Patent 7499366 Method for using dual data-dependent busses for coupling read/write circuits to a memory array
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US Patent 7502251 Phase-change memory device and method of writing a phase-change memory device
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US Patent 7505296 Ternary content addressable memory with block encoding
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US Patent 7505305 Thin film magnetic memory device having a highly integrated memory array
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US Patent 7505327 Method of controlling a semiconductor device by a comparison of times for discharge of bit lines connected to different memory cell arrays
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US Patent 7505330 Phase-change random access memory employing read before write for resistance stabilization
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US Patent 7505331 Programmable logic device with differential communications support
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US Patent 7505344 Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics
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US Patent 7505348 Balanced and bi-directional bit line paths for memory arrays with programmable memory cells
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US Patent 7508714 Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block
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US Patent 7508728 Methods and apparatus to provide refresh for global out of range read requests
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US Patent 7511994 MEM suspended gate non-volatile memory
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US Patent 7511995 Self-boosting system with suppression of high lateral electric fields
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US Patent 7512021 Register configuration control device, register configuration control method, and program for implementing the method
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US Patent 7515450 Nonvolatile semiconductor storage device
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US Patent 7515472 Page buffer circuit of flash memory device and program operation method thereof
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US Patent 7515486 Multimode data buffer and method for controlling propagation delay time
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US Patent 7518902 Resistive memory device and method for writing to a resistive memory cell in a resistive memory device
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US Patent 7518940 Control circuit for stable exit from power-down mode
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US Patent 7522448 Controlled pulse operations in non-volatile memory
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US Patent 7522458 Memory and method of controlling access to memory
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US Patent 7529126 Nonvolatile memory device and semiconductor device
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US Patent 7532523 Memory chip with settable termination resistance circuit
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US Patent 7532532 System and method for hidden-refresh rate modification
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US Patent 7535744 Semiconductor integrated circuit and IC card system having internal information protection
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US Patent 7535778 Semiconductor memory device with memory cells, each having bit registering layer in addition to a memory layer and method of driving the same
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US Patent 7545662 Method and system for magnetic shielding in semiconductor integrated circuit
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US Patent 7545665 High yielding, voltage, temperature, and process insensitive lateral poly fuse memory
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US Patent 7545685 High voltage switch circuit having boosting circuit and flash memory device including the same
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US Patent 7548466 Flash memory device and voltage generating circuit for the same
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US Patent 7548474 Device for reading out a memory cell including a regulating circuit with parallel switching elements, and method
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US Patent 7548484 Semiconductor memory device having column decoder
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US Patent 7551489 Multi-level memory cell sensing
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US Patent 7551502 Semiconductor device
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US Patent 7551513 Semiconductor memory device and method of controlling sub word line driver thereof
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US Patent 7554867 Capacitor boost sensing
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US Patent 7554877 Apparatus and method for data outputting
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US Patent 7558103 Magnetic switching element and signal processing device using the same
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US Patent 7558108 3-bit NROM flash and method of operating same
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US Patent 7558149 Method and apparatus to control sensing time for nonvolatile memory
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US Patent 7561482 Defective block isolation in a non-volatile memory system
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US Patent 7567463 Sense amplifier circuit in multi-level non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node
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US Patent 7570503 Ternary content addressable memory (TCAM) cells with low signal line numbers
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US Patent 7570525 Semiconductor memory device with adjustable selected work line potential under low voltage condition
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US Patent 7580301 Method control circuit performing adjustable data delay operation based upon phase difference between data strobe signal and clock signal, and associated method
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US Patent 7580311 Reduced area high voltage switch for NVM
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US Patent 7583537 Recording device and HDD built-in recording device
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US Patent 7589989 Method for protecting memory cells during programming
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US Patent 7593278 Memory element with thermoelectric pulse
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US Patent 7593280 Semiconductor memory device operating with a lower voltage for peripheral area in power saving mode
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US Patent 7596031 Faster programming of highest multi-level state for non-volatile memory
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US Patent 7596037 Independent bi-directional margin control per level and independently expandable reference cell levels for flash memory sensing
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US Patent 7599220 Charge trapping memory and accessing method thereof
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US Patent 7599231 Adaptive regulator for idle state in a charge pump circuit of a memory device
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US Patent 7602653 Multimode data buffer and method for controlling propagation delay time
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US Patent 7606055 Memory architecture and cell design employing two access transistors
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US Patent 7606079 Reducing power consumption during read operations in non-volatile storage
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US Patent 7606086 Nonvolatile semiconductor memory device
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US Patent 7606091 Method for non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage
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US Patent 7609540 Serial bus controller using nonvolatile ferroelectric memory
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US Patent 7613058 Radiation hardening, detection and protection design methods and circuit examples thereof
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US Patent 7613063 Internal power voltage generating circuit in semiconductor memory device
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US Patent 7619937 Semiconductor memory device with reset during a test mode
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US Patent 7623408 Semiconductor memory device comprising data path controller and related method
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US Patent 7626842 Photon-based memory device and method thereof
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US Patent 7630223 Memory device and method of arranging signal and power lines
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US Patent 7639522 Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device
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US Patent 7639529 Non-volatile memory devices that utilize mirror-image programming techniques to inhibit program coupling noise and methods of programming same
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US Patent 7639544 Non-volatile semiconductor memory
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US Patent 7639548 Semiconductor device having variable parameter selection based on temperature and test method
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US Patent 7639557 Configurable random-access-memory circuitry
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US Patent 7646632 Integrated circuit for setting a memory cell based on a reset current distribution
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US Patent 7646641 NAND flash memory with nitride charge storage gates and fabrication process
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US Patent 7649772 Memory and method for programming in multiple storage region multi-level cells
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US Patent 7649786 Non-volatile memory architecture and method, in particular of the EEPROM type
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US Patent 7649801 Semiconductor memory apparatus having column decoder for low power consumption
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US Patent 7652949 Memory module and register with minimized routing path
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US Patent 7656699 Radiation-hardened programmable device
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US Patent 7660164 Method for estimating threshold voltage of semiconductor device
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US Patent 7660167 Memory device and method for fast cross row data access
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US Patent 7660173 Semiconductor memory device and operating method with hidden write control
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US Patent 7663935 Semiconductor memory device with adjustable I/O bandwidth
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US Patent 7672158 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control
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US Patent 7675799 Method of operating a memory cell, memory cell and memory unit
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US Patent 7679947 Semiconductor devices with source and bulk coupled to separate voltage supplies
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US Patent 7679983 Address path circuit with row redundant scheme
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US Patent 7684226 Method of making high forward current diodes for reverse write 3D cell
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US Patent 7684243 Reducing read failure in a memory device
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US Patent 7684265 Redundant cross point switching system and method
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US Patent 7684271 High integrated open bit line structure semiconductor memory device with precharge units to reduce interference or noise
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US Patent 7684277 Non-volatile memory device with controlled application of supply voltage
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US Patent 7684279 Semiconductor memory device including distributed data input/output lines
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US Patent 7688635 Current sensing for Flash
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US Patent 7688652 Storage of data in memory via packet strobing
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US Patent 7688657 Apparatus and method for generating test signals after a test mode is completed
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US Patent 7688664 Electrical fuse circuit, memory device and electronic part
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US Patent 7692943 Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells
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US Patent 7692954 Apparatus and method for integrating nonvolatile memory capability within SRAM devices
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US Patent 7692969 Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell
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US Patent 7697319 Non-volatile memory device including bistable circuit with pre-load and set phases and related system and method
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US Patent 7697329 Methods and apparatus for using a configuration array similar to an associated data array
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US Patent 7697343 Circuit and method for pre-charging from both ends of an array in a read operation in NAND flash memory
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US Patent 7697355 Semiconductor memory and system with matching characteristics of signal supplied to a dummy signal line and a real signal line
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US Patent 7697366 Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
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US Patent 7697372 Access to printing material container
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US Patent 7701746 Method of making memory cell with voltage modulated sidewall poly resistor
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US Patent 7706197 Storage device and control method of storage device
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US Patent 7706198 Multi-chip and repairing method based on remaining redundancy cells
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US Patent 7706201 Integrated circuit with Resistivity changing memory cells and methods of operating the same
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US Patent 7706202 Semiconductor device having electrical fuses with less power consumption and interconnection arrangement
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US Patent 7710807 Sense amplifiers having MOS transistors therein with different threshold voltages and/or that support different threshold voltage biasing
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US Patent 7715226 Memory device including electrical circuit configured to provide reversible bias across the PMC memory cell to perform erase and write functions
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US Patent 7715248 Phase-change TaN resistor based triple-state/multi-state read only memory
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US Patent 7719897 Program verification for non-volatile memory
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US Patent 7719900 Semiconductor storage device having memory cell for storing data by using difference in threshold voltage
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US Patent 7719912 Semiconductor memory device for sensing voltages of bit lines in high speed
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US Patent 7724559 Self-referenced match-line sense amplifier for content addressable memories
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US Patent 7724575 Page-buffer and non-volatile semiconductor memory including page buffer
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US Patent 7724592 Internal data comparison for memory testing
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US Patent 7724594 Leakage current control device of semiconductor memory device
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US Patent 7733736 Semiconductor memory device for driving a word line
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US Patent 7742346 Voltage booster and memory structure using the same
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US Patent 7742356 Semiconductor memory device having a refresh cycle changing circuit
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US Patent 7746686 Partitioned random access and read only memory
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US Patent 7751218 Self-referenced match-line sense amplifier for content addressable memories
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US Patent 7751236 MEM suspended gate non-volatile memory
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US Patent 7751276 Semiconductor memory device capable of performing page mode operation
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US Patent 7755934 Resistance change memory device
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US Patent 7755938 Method for reading a memory array with neighbor effect cancellation
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US Patent 7760560 High voltage switch circuit having boosting circuit and flash memory device including the same
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US Patent 7760561 Circuit and method for outputting data in semiconductor memory apparatus
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US Patent 7760574 Flash memory controller utilizing multiple voltages and a method of use
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US Patent 7764536 Method and system for providing a sense amplifier and drive circuit for spin transfer torque magnetic random access memory
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US Patent 7768856 Control of temperature slope for band gap reference voltage in a memory device
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US Patent 7773423 Low power, CMOS compatible non-volatile memory cell and related method and memory array
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US Patent 7773425 Nonvolatile semiconductor memory, method for reading the same, and microprocessor
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US Patent 7773443 Current sensing method and apparatus for a memory array
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US Patent 7773444 Semiconductor memory device and data write and read methods thereof
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US Patent 7777271 System and method for providing low cost high endurance low voltage electrically erasable programmable read only memory
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US Patent 7778081 Method for performing operations by applying periodic voltage pulses to control gate of an ono memory cell
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US Patent 7778088 Erasing flash memory using adaptive drain and/or gate bias
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US Patent 7782681 Operation method of flash memory device capable of down-shifting a threshold voltage distribution of memory cells in a post-program verify operation
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US Patent 7782684 Semiconductor memory device operating in a test mode and method for driving the same
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US Patent 7791974 Recovery of existing SRAM capacity from fused-out blocks
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US Patent 7804702 Ferroelectric memory cell with access transmission gate
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US Patent 7804718 Partial block erase architecture for flash memory
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US Patent 7813158 Recordable electrical memory
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US Patent 7813195 Method for testing semiconductor memory device
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US Patent 7813204 Method and system for memory thermal load sharing using memory on die termination
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US Patent 7813208 Motherboard with voltage regulator for supporting DDR2 memory modules and DDR3 memory modules
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US Patent 7817469 Drift compensation in a flash memory
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US Patent 7817470 Non-volatile memory serial core architecture
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US Patent 7817482 Memory device having data paths with multiple speeds
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US Patent 7817487 Motherboard with voltage regulator for supporting DDR2 memory modules and DDR3 memory modules
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US Patent 7821813 Nanowire memory device and method of manufacturing the same
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US Patent 7821834 Nonvolatile memory devices that utilize dummy memory cells to improve data reliability in charge trap memory arrays
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US Patent 7843722 Nonvolatile semiconductor memory device and programming method thereof
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US Patent 7843724 Nonvolatile semiconductor memory and data reading method
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US Patent 7843728 Nonvolatile semiconductor storage device
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US Patent 7843746 Method and device for redundancy replacement in semiconductor devices using a multiplexer
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US Patent 7843748 Test apparatus of semiconductor integrated circuit and method using the same
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US Patent 7843751 Semiconductor memory device comprising sense amplifier having P-type sense amplifier and N-type sense amplifiers with different threshold voltages
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US Patent 7848131 High speed ferroelectric random access memory
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US Patent 7852691 Semiconductor memory device using dynamic data shift redundancy system and method of relieving failed area using same system
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US Patent 7859905 Semiconductor storage device and method of manufacturing the same
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US Patent 7859907 Non-volatile semiconductor memory
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US Patent 7864559 Dram memory device with improved refresh characteristic
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US Patent 7864570 Self-boosting system with suppression of high lateral electric fields
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US Patent 7864597 Method and circuit for controlling generation of a boosted voltage in devices receiving dual supply voltages
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US Patent 7864601 Semiconductor memory device and method for generating pipe-in signal thereof
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US Patent 7864615 Flash memory controller utilizing multiple voltages and a method of use
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US Patent 7869261 Semiconductor memory which enables reliable data writing with low supply voltage by improving the conductance via access transistors during write operation
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US Patent 7869287 Circuit for locking a delay locked loop (DLL) and method therefor
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US Patent 7876597 NAND-structured series variable-resistance material memories, processes of forming same, and methods of using same
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US Patent 7876598 Apparatus and method for determining a memory state of a resistive n-level memory cell and memory device
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US Patent 7876600 SRAM and method of controlling the SRAM
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US Patent 7881137 Read assist for memory circuits with different precharge voltage levels for bit line pair
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US Patent 7885103 Non-volatile electromechanical configuration bit array
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US Patent 7889579 Using differential data strobes in non-differential mode to enhance data capture window
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US Patent 7894290 Method and apparatus for performing internal hidden refreshes while latching read/write commands, address and data information for later operation
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US Patent 7898867 Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell
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US Patent 7898885 Analog sensing of memory cells in a solid state memory device
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US Patent 7911867 Semiconductor memory device capable of performing per-bank refresh
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US Patent 7920413 Apparatus and method for writing data to phase-change memory by using power calculation and data inversion
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US Patent 7929329 Memory bank signal coupling buffer and method
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US Patent 7929355 Memory device performing write leveling operation
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US Patent 7933136 Non-volatile memory cell with multiple resistive sense elements sharing a common switching device
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US Patent 7933142 Semiconductor memory cell and array using punch-through to program and read same
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US Patent 7933150 Nonvolatile semiconductor memory device and programming method thereof
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US Patent 7936624 Reduced power bitline precharge scheme for low power applications in memory devices
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US Patent 7936625 Pipeline sensing using voltage storage elements to read non-volatile memory cells
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US Patent 7936636 Semiconductor memory device and method for reducing current consumption by controlling toggling of clock
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US Patent 7940557 Non-volatile electromechanical configuration bit array
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US Patent 7940562 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control
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US Patent 7944733 Static random access memory (SRAM) of self-tracking data in a read operation, and method thereof
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US Patent 7944739 Phase change memory device with bit line discharge path
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US Patent 7944749 Method of low voltage programming of non-volatile memory cells
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US Patent 7944763 Semiconductor memory device for preventing mal-operation induced by misrecognizing addresses/data as commands and operating method thereof
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US Patent 7948807 Semiconductor memory device having a current consumption reduction in a data write path
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US Patent 7952956 Variable resistance memory device and system
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US Patent 7957189 Drift compensation in a flash memory
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US Patent 7957193 Semiconductor memory device including two different nonvolatile memories
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US Patent 7957207 Programmable resistance memory with interface circuitry for providing read information to external circuitry for processing
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US Patent 7961546 Memory power management systems and methods
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US Patent 7961548 Semiconductor memory device having column decoder
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US Patent 7965542 Magnetic random access memory and write method of the same
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US Patent 7965582 Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus
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US Patent 7974115 One-time programmable devices including chalcogenide material and electronic systems including the same
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US Patent 7974130 Semiconductor memory device and method for erasing the same
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US Patent 7974144 Memory with tunable sleep diodes
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US Patent 7978536 Semiconductor memory device and method of operating the same
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US Patent 7978556 On-chip temperature sensor
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US Patent 7983071 Dual node access storage cell having buffer circuits
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US Patent 7983079 Nonvolatile semiconductor memory device and programming method thereof
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US Patent 7983098 Adaptive regulator for idle state in a charge pump circuit of a memory device
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US Patent 7986552 Nonvolatile memory device and method of operation to program/read data by encoding/decoding using actual data and random data for program/read operation
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US Patent 7986575 Semiconductor memory device and redundancy method therefor
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US Patent 7990763 Memory with weighted multi-page read
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US Patent 7990765 Least significant bit page recovery method used in multi-level cell flash memory device
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US Patent 7995371 Threshold device for a memory array
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US Patent 7995372 Resistance change memory device with stabilizing circuit coupled in series with selected resistance change memory cell
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US Patent 7995381 Method of programming resistivity changing memory
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US Patent 7995399 NAND memory device and programming methods
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US Patent 7995404 Semiconductor IC device and data output method of the same
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US Patent 8000134 Off-die charge pump that supplies multiple flash devices
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US Patent 8004871 Semiconductor memory device including FET memory elements
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US Patent 8004886 Apparatus and method of multi-bit programming
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US Patent 8004888 Flash mirror bit architecture using single program and erase entity as logical cell
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US Patent 8004889 Semiconductor memory device capable of lowering a write voltage
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US Patent 8004899 Memory array and method of operating a memory
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US Patent 8004905 Nonvolatile memory system, semiconductor memory and writing method
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US Patent 8004922 Power island with independent power characteristics for memory and logic
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US Patent RE42659 Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed
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US Patent 8009459 Circuit for high speed dynamic memory
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US Patent 8009481 System and method for bit-line control
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US Patent 8009497 Auto-refresh control circuit and a semiconductor memory device using the same
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US Patent 8009481 System and method for bit-line control
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US Patent 8009497 Auto-refresh control circuit and a semiconductor memory device using the same
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US Patent 8009459 Circuit for high speed dynamic memory
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edited on 8 Dec, 2021
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US Patent 8004871 Semiconductor memory device including FET memory elements
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edited on 8 Dec, 2021
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US Patent 8004922 Power island with independent power characteristics for memory and logic
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US Patent 8004905 Nonvolatile memory system, semiconductor memory and writing method
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US Patent 8004899 Memory array and method of operating a memory
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US Patent 8004888 Flash mirror bit architecture using single program and erase entity as logical cell
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Patent primary examiner of
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US Patent 8004889 Semiconductor memory device capable of lowering a write voltage
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edited on 8 Dec, 2021
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US Patent 8004886 Apparatus and method of multi-bit programming
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edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 8000134 Off-die charge pump that supplies multiple flash devices
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edited on 8 Dec, 2021
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US Patent 7995399 NAND memory device and programming methods
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US Patent 7995404 Semiconductor IC device and data output method of the same
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US Patent 7995381 Method of programming resistivity changing memory
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US Patent 7995371 Threshold device for a memory array
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US Patent 7990765 Least significant bit page recovery method used in multi-level cell flash memory device
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US Patent 7990763 Memory with weighted multi-page read

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