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US Patent 11948930 Semiconductor package and method of manufacturing the same

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 US Patent 11948930 Semiconductor package and method of manufacturing the same

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Patent abstract

A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.

Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
119489300
Patent Inventor Names
Chen-Hua Yu0
Chin-Chuan Chang0
Szu-Wei Lu0
Date of Patent
April 2, 2024
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Patent Application Number
170975790
Date Filed
November 13, 2020
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Patent Citations
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US Patent 8361842 Embedded wafer-level bonding approaches
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US Patent 8680647 Packages with passive devices and methods of forming the same
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US Patent 8703542 Wafer-level packaging mechanisms
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US Patent 8759964 Wafer level package structure and fabrication methods
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US Patent 8778738 Packaged semiconductor devices and packaging devices and methods
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US Patent 8785299 Package with a fan-out structure and method of forming the same
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US Patent 8803306 Fan-out package structure and methods for forming the same
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US Patent 8809996 Package with passive devices and method of forming the same
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US Patent 8829676 Interconnect structure for wafer level package
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US Patent 8877554 Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
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US Patent 8993380 Structure and method for 3D IC package
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US Patent 9281254 Methods of forming integrated circuit package
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US Patent 9299649 3D packages and methods for forming the same
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US Patent 9372206 Testing of semiconductor chips with microbumps
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US Patent 9425126 Dummy structure for chip-on-wafer-on-substrate
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US Patent 9443783 3DIC stacking device and method of manufacture
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US Patent 9461018 Fan-out PoP structure with inconsecutive polymer layer
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US Patent 9496189 Stacked semiconductor devices and methods of forming same
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US Patent 9666502 Discrete polymer in fan-out packages
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US Patent 9735131 Multi-stack package-on-package structures
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US Patent 10153175 Metal oxide layered structure and methods of forming the same
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US Patent 10163750 Package structure for heat dissipation
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US Patent 10267990 Hybrid interconnect device and method
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US Patent 10475762 3DIC structure and method of manufacturing the same
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US Patent 10529690 Package structures and methods of forming the same
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US Patent 10535633 Chip package having die structures of different heights and method of forming same
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US Patent 10727198 Semiconductor package and method manufacturing the same
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US Patent 10840129 Semiconductor package and method
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US Patent 10867962 Packaging process and manufacturing method
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US Patent 10930580 Semiconductor device and method of manufacture
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US Patent 10950550 Semiconductor package with through bridge die connections
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US Patent 10978424 Semiconductor device and manufacturing method thereof
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Patent Primary Examiner
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Anthony Ho
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CPC Code
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H01L 2924/00014
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H01L 2924/00012
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H01L 25/50
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H01L 21/568
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H01L 2924/00
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