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Leigh Marie Garbowski

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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
Edits made to:
Infobox (-169 properties)
Infobox
Patent primary examiner of
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US Patent 7376931 Method for providing layout design and photo mask
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US Patent 7389480 Content based yield prediction of VLSI designs
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US Patent 7389486 Arc routing system and method
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US Patent 7389487 Dedicated interface architecture for a hybrid integrated circuit
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US Patent 7395521 Method and apparatus for translating an imperative programming language description of a circuit into a hardware description
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US Patent 7398483 Design verification method for programmable logic design
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US Patent 7398495 Method and apparatus for characterizing arrays using cell-based timing elements
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US Patent 7409665 Method for checking return path of printed and CAD apparatus for designing patterns of printed board
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US Patent 7424691 Method for verifying performance of an array by simulating operation of edge cells in a full array model
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US Patent 7424694 Integrated circuit layout device, method thereof and program thereof
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US Patent 7437688 Element routing method and apparatus
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US Patent 7444613 Systems and methods for mapping arbitrary logic functions into synchronous embedded memories
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US Patent 7448010 Methods and mechanisms for implementing virtual metal fill
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US Patent 7451416 Method and system for designing an electronic circuit
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US Patent 7454725 Apparatus and computer readable medium having program for analyzing distributed constant in a transmission line
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US Patent 7458039 Electronic stream processing circuit with locally controlled parameter updates, and method of designing such a circuit
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US Patent 7458053 Method for generating fill and cheese structures
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US Patent 7458056 Effective proximity effect correction methodology
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US Patent 7464355 Timing analyzing method and apparatus for semiconductor integrated circuit
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US Patent 7464362 Method and apparatus for performing incremental compilation
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US Patent 7469395 Wiring optimizations for power
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US Patent 7472371 Description style conversion method, program, and system of logic circuit
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US Patent 7475367 Memory power models related to access information and methods thereof
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US Patent 7478348 Method and apparatus of rapid determination of problematic areas in VLSI layout by oriented sliver sampling
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US Patent 7480880 Method, system, and program product for computing a yield gradient from statistical timing
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US Patent 7484186 Method for designing a system LSI
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US Patent 7487482 Method and system for evaluating a constraint of a sequential cell
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US Patent 7487483 Clock model for formal verification of a digital circuit description
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US Patent 7487485 Methods and apparatus for design entry and synthesis of digital circuits
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US Patent 7487489 Calculation system for inverse masks
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US Patent 7487492 Method for increasing manufacturability of a circuit layout
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US Patent 7493584 Methods and apparatus for selective comment assertion
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US Patent 7496867 Cell library management for power optimization
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US Patent 7500216 Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines
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US Patent 7500218 Lithographic apparatus, method, and computer program product for generating a mask pattern and device manufacturing method using same
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US Patent 7503020 IC layout optimization to improve yield
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US Patent 7506300 Apparatus and method for breaking up and merging polygons
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US Patent 7512913 Designing apparatus, designing method, and program thereof
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US Patent 7512920 Method and program for designing semiconductor integrated circuits, and semiconductor integrated circuit designing apparatus
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US Patent 7512922 Methods of structured placement of a circuit design
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US Patent 7516429 System for analyzing an electronic circuit described by characterization data
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US Patent 7519942 Pattern specification method and pattern specification apparatus
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US Patent 7523437 Pattern-producing method for semiconductor device
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US Patent 7526744 Integrated circuit design method for efficiently generating mask data
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US Patent 7533356 Parameter adjusting device and parameter adjusting means
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US Patent 7539959 Library creating apparatus and method, and recording medium recording library creating program thereon
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US Patent 7539968 Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints
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US Patent 7543263 Automatic trace shaping method
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US Patent 7543265 Method for early logic mapping during FPGA synthesis
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US Patent 7546567 Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip
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US Patent 7549139 Tuning programmable logic devices for low-power design implementation
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US Patent 7552413 System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model
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US Patent 7552416 Calculation system for inverse masks
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US Patent 7555734 Processing constraints in computer-aided design for integrated circuits
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US Patent 7555739 Method and apparatus for maintaining synchronization between layout clones
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US Patent 7562323 System, method and computer program product for handling small aggressors in signal integrity analysis
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US Patent 7568173 Independent migration of hierarchical designs with methods of finding and fixing opens during migration
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US Patent 7568174 Method for checking printability of a lithography target
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US Patent 7571403 Circuit verification
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US Patent 7571421 System, method, and computer-readable medium for performing data preparation for a mask design
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US Patent 7574682 Yield analysis and improvement using electrical sensitivity extraction
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US Patent 7574685 Method, system, and article of manufacture for reducing via failures in an integrated circuit design
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US Patent 7584445 Sequence-pair creating apparatus and sequence-pair creating method
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US Patent 7590961 Integrated circuit with signal skew adjusting cell selected from cell library
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US Patent 7590968 Methods for risk-informed chip layout generation
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US Patent 7594209 Method for incorporating Miller capacitance effects in digital circuits for an accurate timing analysis
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US Patent 7594212 Automatic pin placement for integrated circuits to aid circuit board design
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US Patent RE40925 Methods for automatically pipelining loops
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US Patent 7596776 Light intensity distribution simulation method and computer program product
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US Patent 7600208 Automatic placement of decoupling capacitors
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US Patent 7603635 Asynchronous, multi-rail digital circuit with gating and gated sub-circuits and method for designing the same
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US Patent 7610567 Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs
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US Patent 7617468 Method for automatic maximization of coverage in constrained stimulus driven simulation
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US Patent 7620921 IC chip at-functional-speed testing with process coverage evaluation
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US Patent 7620929 Programmable logic device having a programmable selector circuit
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US Patent 7627846 Method and apparatus for automatically shaping traces on surface of substrate of semiconductor package by using computation
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US Patent 7636908 Generation of a specification of a network packet processor
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US Patent 7636909 Automatically generating multithreaded datapaths
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US Patent 7644388 Method for reducing layout printability effects on semiconductor device performance
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US Patent 7653886 Crosslinking of netlists
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US Patent 7653889 Method and apparatus for repeat execution of delay analysis in circuit design
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US Patent 7657851 Device, system, and method for correction of integrated circuit design
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US Patent 7657862 Synchronous elastic designs with early evaluation
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US Patent 7657865 Computer-readable recording medium recording a mask data generation program, mask data generation method, mask fabrication method, exposure method, and device manufacturing method
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US Patent 7661081 Content based yield prediction of VLSI designs
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US Patent 7661085 Method and system for performing global routing on an integrated circuit design
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US Patent 7669161 Minimizing effects of interconnect variations in integrated circuit designs
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US Patent 7669166 Generation of a specification of a processor of network packets
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US Patent 7669173 Semiconductor mask and method of making same
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US Patent 7673262 System and method for product yield prediction
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US Patent 7673280 Optical proximity correction (OPC) processing method for preventing the occurrence of off-grid
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US Patent 7676776 Spare gate array cell distribution analysis
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US Patent 7676778 Circuit design optimization of integrated circuit based clock gated memory elements
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US Patent 7676780 Techniques for super fast buffer insertion
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US Patent 7685547 Method, system, and computer program product for generating automated assumption for compositional verification
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US Patent 7685557 Radiation mask with spatially variable transmissivity
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US Patent 7689954 Efficient statistical timing analysis of circuits
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US Patent 7689964 System and method for routing connections
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US Patent 7694253 Automatically generating an input sequence for a circuit design using mutant-based verification
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US Patent 7694269 Method for positioning sub-resolution assist features
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US Patent 7698681 Method for radiation tolerance by logic book folding
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US Patent 7698682 Writing error verification method of pattern writing apparatus and generation apparatus of writing error verification data for pattern writing apparatus
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US Patent 7703069 Three-dimensional mask model for photolithography simulation
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US Patent 7707528 System and method for performing verification based upon both rules and models
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US Patent 7707531 Method and program for designing semiconductor integrated circuits, and semiconductor integrated circuit designing apparatus
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US Patent 7712058 System and method for design, procurement and manufacturing collaboration
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US Patent 7712067 Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints
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US Patent 7716618 Method and system for designing semiconductor circuit devices to reduce static power consumption
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US Patent 7725858 Providing a moat capacitance
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US Patent 7725870 Method for radiation tolerance by implant well notching
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US Patent 7730438 Methods and apparatuses for designing multiplexers
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US Patent 7739626 Method and apparatus for small die low power system-on-chip design with intelligent power supply chip
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US Patent 7739628 Synchronous to asynchronous logic conversion
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US Patent 7739641 Integrated circuit having a clock tree
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US Patent 7739644 Methods, systems, and computer program products for grid-morphing techniques in placement, floorplanning, and legalization
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US Patent 7739646 Analog and mixed signal IC layout system
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US Patent 7761838 Method for fabricating a semiconductor device having an extended stress liner
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US Patent 7774726 Dummy fill for integrated circuits
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US Patent 7784014 Generation of a specification of a network packet processor
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US Patent 7788623 Composite wire indexing for programmable logic devices
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US Patent 7797666 Systems and methods for mapping arbitrary logic functions into synchronous embedded memories
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US Patent 7810055 Design independent correlation data storage for use with physical design of programmable logic devices
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US Patent 7818694 IC layout optimization to improve yield
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US Patent 7818702 Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates
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US Patent 7823107 Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design
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US Patent 7831949 Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit
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US Patent 7831951 Task concurrency management design method
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US Patent 7840930 Signal connection program, method, and device of hierarchical logic circuit
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US Patent 7844941 Charged particle beam exposure method and charged particle beam exposure device
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US Patent 7861198 Distorted waveform propagation and crosstalk delay analysis using multiple cell models
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US Patent 7861199 Method and apparatus for incrementally computing criticality and yield gradient
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US Patent 7870526 Aid apparatus, computer-readable recording medium in which design aid program is stored, and interactive design aid apparatus
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US Patent 7873928 Hierarchical analog IC placement subject to symmetry, matching and proximity constraints
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US Patent 7877718 Analog IC placement using symmetry-islands
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US Patent 7882466 Noise checking method and apparatus, and computer-readable recording medium in which noise checking program is stored
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US Patent 7890892 Balanced and bi-directional bit line paths for memory arrays with programmable memory cells
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US Patent 7900171 Electronic stream processing circuit with locally controlled parameter updates, and method of designing such a circuit
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US Patent 7900174 Method and system for characterizing an integrated circuit design
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US Patent 7900182 Method and system for designing an electronic circuit
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US Patent 7904865 Placement driven routing
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US Patent 7904871 Computer-implemented method of optimizing refraction and TIR structures to enhance path lengths in PV devices
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US Patent 7908573 Minimizing effects of interconnect variations in integrated circuit designs
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US Patent 7917879 Semiconductor device with dynamic array section
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US Patent 7921391 Apparatus, method and computer-readable code for automated design of physical structures of integrated circuits
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US Patent 7921404 Method of reusing constraints in PCB designs
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US Patent 7930657 Methods of forming photomasks
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US Patent 7930665 Method and program for designing semiconductor integrated circuit
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US Patent 7945890 Registry for electronic design automation of integrated circuits
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US Patent 7958475 Synthesis of assertions from statements of power intent
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US Patent 7958484 Affinity-based clustering of vectors for partitioning the columns of a matrix
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US Patent 7966582 Method and apparatus for modeling long-range EUVL flare
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US Patent 7966584 Pattern-producing method for semiconductor device
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US Patent 7966586 Intelligent pattern signature based on lithography effects
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US Patent 7966593 Integrated circuit design system, method, and computer program product that takes into account the stability of various design signals
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US Patent 7971163 Property generating apparatus, property generating method and program
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US Patent 7971177 Design tool for charge trapping memory using simulated programming operations
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US Patent 7975253 Power supply noise analysis model generating method and power supply noise analysis model generating apparatus
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US Patent 7979834 Predicting timing degradations for data signals in an integrated circuit
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US Patent 7979835 Method of estimating resource requirements for a circuit design
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US Patent 7984395 Hierarchical compression for metal one logic layer
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US Patent 7984406 Timing verification method and apparatus
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US Patent 7987434 Calculation system for inverse masks
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US Patent 7987435 Pattern verification method, program thereof, and manufacturing method of semiconductor device
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US Patent 7987439 Method and apparatus for analyzing circuit model by reduction and computer program product for analyzing the circuit model
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US Patent 8001492 Evaluation method for interconnects interacted with integrated-circuit manufacture
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US Patent 8001508 Method and system for analyzing input/output simultaneous switching noise
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US Patent 8001515 Simultaneous optimization of analog design parameters using a cost function of responses
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US Patent 8006213 Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew
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US Patent 8010922 Automated method for buffering in a VLSI design
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8010922 Automated method for buffering in a VLSI design
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Golden AI
edited on 8 Dec, 2021
Edits on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8001515 Simultaneous optimization of analog design parameters using a cost function of responses
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8001508 Method and system for analyzing input/output simultaneous switching noise
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8001492 Evaluation method for interconnects interacted with integrated-circuit manufacture
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7987434 Calculation system for inverse masks
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7984406 Timing verification method and apparatus
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7984395 Hierarchical compression for metal one logic layer
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7979834 Predicting timing degradations for data signals in an integrated circuit
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7979835 Method of estimating resource requirements for a circuit design
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7971177 Design tool for charge trapping memory using simulated programming operations
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7971163 Property generating apparatus, property generating method and program
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7966586 Intelligent pattern signature based on lithography effects
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7966582 Method and apparatus for modeling long-range EUVL flare
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7966584 Pattern-producing method for semiconductor device

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