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Sun J Lin

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Patent primary examiner of
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US Patent 11173802 Method for controlling a charging process of a vehicle at a charging post using first and second authorisation verification
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US Patent 7337420 Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models
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US Patent 11180044 Electric vehicle cooling system
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US Patent 11183847 Stationary storage device for temporarily storing electric energy in an electric supply grid, operating method, and retrofitting module for the stationary storage device
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US Patent 11183856 Battery system, electrically-powered vehicle and control method for electrically-powered vehicle
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US Patent 11184999 Charging column
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US Patent 7386821 Primitive cell method for front end physical design
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US Patent 7386827 Building a simulation environment for a design block
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US Patent 7389484 Method and apparatus for tiling memories in integrated circuit layout
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US Patent 7398491 Method for fast incremental calculation of an impact of coupled noise on timing
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US Patent 7401301 Circuit design support method, device thereof, and circuit design support program
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US Patent 7404160 Method and system for hardware based reporting of assertion information for emulation and hardware acceleration
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US Patent 7404166 Method and system for mapping netlist of integrated circuit to design
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US Patent 7409661 Computer-aided thermal relief pad design system and method
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US Patent 7409664 Architecture and interconnect scheme for programmable logic circuits
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US Patent 7412677 Detecting reducible registers
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US Patent 7415680 Power managers for an integrated circuit
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US Patent 7415695 System for search and analysis of systematic defects in integrated circuits
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US Patent 7418683 Constraint assistant for circuit design
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US Patent 7426710 Standard cell library having cell drive strengths selected according to delay
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US Patent 7428713 Accelerated design optimization
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US Patent 7428718 Enhanced incremental placement during physical synthesis
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US Patent 7434181 Debugger of an electronic circuit manufactured based on a program in hardware description language
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US Patent 7434185 Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data
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US Patent 7434190 Analysis method and analysis apparatus of designing transmission lines of an integrated circuit packaging board
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US Patent 7434191 Router
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US Patent 7434199 Dense OPC
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US Patent 7437694 System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design
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US Patent 7444609 Method of optimizing customizable filler cells in an integrated circuit physical design process
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US Patent 7448003 Signal flow driven circuit analysis and partitioning technique
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US Patent 7448015 Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation
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US Patent 7451411 Integrated circuit design system
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US Patent 7451413 Methods of minimizing leakage current by analyzing post layout information and associated threshold voltage and leakage current
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US Patent 7451427 Bus representation for efficient physical synthesis of integrated circuit designs
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US Patent 7461365 Increased effective flip-flop density in a structured ASIC
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US Patent 7464346 Method for designing phase-lock loop circuits
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US Patent 7469397 Automatic trace determination method and apparatus for automatically determining optimal trace positions on substrate using computation
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US Patent 7469401 Method for using partitioned masks to build a chip
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US Patent 7472361 System and method for generating a plurality of models at different levels of abstraction from a single master model
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US Patent 7472370 Comparing graphical and netlist connections of a programmable logic device
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US Patent 7478357 Versatile bus interface macro for dynamically reconfigurable designs
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US Patent 7480887 Methods and apparatus for defining Manhattan power grid structures beneficial to diagonal signal wiring
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US Patent 7493588 Mixing and matching method and integration system for providing backup strategries for optical environments and method for operating the same
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US Patent 7496872 Library creating device and interconnect capacitance estimation system using the same
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US Patent 7496875 Designing method for designing electronic component
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US Patent 7496877 Electrostatic discharge failure avoidance through interaction between floorplanning and power routing
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US Patent 7496885 Method of compensating for defective pattern generation data in a variable shaped electron beam system
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US Patent 7500211 Unit cell of semiconductor integrated circuit and wiring method and wiring program using unit cell
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US Patent 7503023 Efficient method for locating a short circuit
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US Patent 7503024 Method for hierarchical VLSI mask layout data interrogation
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US Patent 7506292 Method for clock synchronization validation in integrated circuit design
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US Patent 7506296 Programmable logic device design tool with support for variable predriver power supply levels
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US Patent 7509610 Timing analysis for programmable logic devices fabricated in different Fabs
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US Patent 7516428 Microwave circuit performance optimization by on-chip digital distribution of operating set-point
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US Patent 11186193 System and method for controlling charging power of eco-friendly vehicle
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US Patent 11188995 Electric vehicle rescue system
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US Patent 11190028 Circuitry and apparatuses for monitoring and controlling a battery and configurable batteries
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US Patent 11190044 Charging control method and charging control system using energy generated from solar roof
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US Patent 7523419 Semiconductor integrated device for preventing breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof, design method thereof, designing apparatus method thereof, and maunfacturing apparatus thereof
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US Patent 7523428 Hierarchical signal integrity analysis using interface logic models
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US Patent 7523430 Programmable logic device design tool with simultaneous switching noise awareness
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US Patent 7526740 System and method for automated electronic device design
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US Patent 7530041 System and method for auto-routing jog elimination
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US Patent 7530042 System and method for auto-routing jog elimination
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US Patent 7536668 Determining networks of a tile module of a programmable logic device
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US Patent 7539964 Cell placement taking into account consumed current amount
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US Patent 7539966 Enhanced OP3 algorithms for net cuts, net joins, and probe points for a digital design
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US Patent 7543260 Design supporting system of semiconductor integrated circuit, method of designing semiconductor integrated circuit, and computer readable medium for supporting design of semiconductor integrated circuit
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US Patent 7546573 Semiconductor device pattern generation
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US Patent 7549141 Photomask, photomask manufacturing method, and photomask processing device
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US Patent 7552417 System for search and analysis of systematic defects in integrated circuits
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US Patent RE40855 Integrated circuit having a reduced spacing between a bus and adjacent circuitry
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US Patent 7562332 Disabling unused/inactive resources in programmable logic devices for static power reduction
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US Patent 7565631 Method and system for translating software binaries and assembly code onto hardware
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US Patent 7565636 System for performing verification of logic circuits
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US Patent 7568175 Ramptime propagation on designs with cycles
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US Patent 7568180 Generalization of the photo process window and its application to OPC test pattern design
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US Patent 7571396 System and method for providing swap path voltage and temperature compensation
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US Patent 7571409 Circuit design device and circuit design program
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US Patent 7574679 Generating cores using secure scripts
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US Patent 7574686 Method and system for implementing deterministic multi-processing
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US Patent 7587703 Layout determination method, method of manufacturing semiconductor devices, and computer readable program
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US Patent 7590953 Static timing analysis and dynamic simulation for custom and ASIC designs
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US Patent 7590957 Method and apparatus for fixing best case hold time violations in an integrated circuit design
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US Patent 7590965 Methods of generating a design architecture tailored to specified requirements of a PLD design
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US Patent 7594196 Block interstitching using local preferred direction architectures, tools, and apparatus
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US Patent 7594201 Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code
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US Patent 7596770 Temporal decomposition for design and verification
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US Patent 7600202 Techniques for providing a failures in time (FIT) rate for a product design process
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US Patent 7600207 Stress-managed revision of integrated circuit layouts
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US Patent 7603638 Method and system for modeling statistical leakage-current distribution
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US Patent 7603640 Multilevel IC floorplanner
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US Patent 7607112 Method and apparatus for performing metalization in an integrated circuit process
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US Patent 7610568 Methods and apparatus for making placement sensitive logic modifications
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US Patent 7610574 Method and apparatus for designing fine pattern
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US Patent 7614032 Method for correcting a mask design layout
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US Patent 7614033 Mask data preparation
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US Patent 7617477 Method for selecting and optimizing exposure tool using an individual mask error model
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US Patent 7631283 Methods and apparatus for defining manhattan power grid structures having a reduced number of vias
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US Patent 7634750 Logic diagram display method, program, and apparatus
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US Patent 7647567 System and method for scheduling TRS rules
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US Patent 7650583 Method for determining maximum operating frequency of a filtered circuit
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US Patent 7653890 Modeling resolution enhancement processes in integrated circuit fabrication
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US Patent 7665048 Method and system for inspection optimization in design and production of integrated circuits
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US Patent 7673266 Timing analysis method and apparatus, computer-readable program and computer-readable storage medium
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US Patent 7673269 Automatic trace determination apparatus and method
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US Patent 7673275 Development system for an integrated circuit having standardized hardware objects
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US Patent 7681161 Circuit delay analyzer, circuit delay analyzing method, and computer product
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US Patent 7685544 Testing pattern sensitive algorithms for semiconductor design
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US Patent 7685551 Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment
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US Patent 7689945 Product reliability analysis
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US Patent 7689946 High-performance FET device layout
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US Patent 7694254 Method, computer program product, and apparatus for static timing with run-time reduction
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US Patent 7694258 Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout
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US Patent 7694264 Pulse link and apparatus for transmitting data and timing information on a single line
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US Patent 7698672 Methods of minimizing leakage current
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US Patent 7698679 Method and apparatus for automatic routing yield optimization
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US Patent 7703054 Circuit emulation and debugging method
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US Patent 7703055 Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole
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US Patent 7703060 Stitched IC layout methods, systems and program product
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US Patent 7707535 Stitched IC chip layout design structure
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US Patent 7721233 Efficient large-scale full-wave simulation
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US Patent 7725857 Method for optimizing organizational floor layout and operations
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US Patent 7725859 Methods and mechanisms for inserting metal fill data
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US Patent 7725862 Signal routing on redistribution layer
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US Patent 7730433 Analog design retargeting
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US Patent 7730436 Verification using simultaneous and inductive SAT algorithms
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US Patent 7735033 MOSFET modeling for IC design accurate for high frequencies
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US Patent 7735039 Methods of estimating net delays in tile-based PLD architectures
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US Patent 7735049 Mask network design for scan-based integrated circuits
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US Patent 7739625 Method for controlling peak current of a circuit having a plurality of registers
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US Patent 7739640 Method and apparatus for static timing analysis in the presence of a coupling event and process variation
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US Patent 7752578 Automatic voltage drop optimization
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US Patent 7752589 Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design
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US Patent 7761819 System and method of modification of integrated circuit mask layout
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US Patent 7761820 Automated migration of analog and mixed-signal VLSI design
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US Patent 7761824 System and method to generate an IC layout using simplified manufacturing rule
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US Patent 7761826 Method and system for crosstalk analysis
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US Patent 7761834 Interactive schematic for use in analog, mixed-signal, and custom digital circuit design
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US Patent 7765498 Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist
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US Patent 7765504 Design method and system for minimizing blind via current loops
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US Patent 7765509 Auto connection assignment system and method
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US Patent 7770141 Computer recording medium for storing program of checking design rule of layout
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US Patent 7774727 Layout making equipment of semiconductor integrated circuit, method of making layout of semiconductor integrated circuit and process of manufacture of semiconductor device
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US Patent 7783998 Method and system for prototyping electronic devices with multi-configuration CHIP carriers
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US Patent 7788616 Method and system for performing heuristic constraint simplification
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US Patent 7788619 Memories, memory compiling systems and methods for the same
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US Patent 7793235 Method and circuit for matching semiconductor device behavior
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US Patent 7793242 Method and system for performing heuristic constraint simplification
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US Patent RE41704 Timing signal generation for charge-coupled device
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US Patent 7797663 Conductive dome probes for measuring system level multi-GHZ signals
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US Patent 7802223 Method and system for configurable contacts for implementing different bias designs of an integrated circuit device
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US Patent 7805687 One-time programmable (OTP) memory cell
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US Patent 7805692 Method for local hot spot fixing
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US Patent 7805696 Method for fast identification of available reference designators in a design automation system
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US Patent 7810054 Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point
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US Patent 7810066 Irradiation pattern data generation method, mask fabrication method, and plotting system
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US Patent 7814444 Scan compression circuit and method of design therefor
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US Patent 7814445 Circuit wiring interference analysis device, interference analysis program, database used in interference analysis device, and asymmetrically connected line model
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US Patent 7814450 Active skew control of a digital phase-lock loop using delay lock-loops
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US Patent 7814451 Incremental relative slack timing force model
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US Patent 7823116 Hierarchical analog layout synthesis and optimization for integrated circuits
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US Patent 7831939 Semiconductor integrated circuit device featuring processed minimum circuit pattern, and design method therefor
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US Patent 7831947 Semiconductor layout design apparatus, semiconductor layout design method and computer readable medium
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US Patent 7844925 System and method for power domain optimization
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US Patent 7849423 Method of verifying photomask data based on models of etch and lithography processes
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US Patent 7849425 Generating self-checking test cases from a reduced case analysis graph using path inheritance
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US Patent 7849434 Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit
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US Patent 7853913 Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit
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US Patent 7853918 Reverse dummy insertion algorithm
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US Patent 7861194 Method and apparatus for calculating wiring capacitance, and computer product
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US Patent 7861201 Method for verifying timing of a circuit with crosstalk victim and aggressor
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US Patent 7865866 Method of inspecting mask using aerial image inspection apparatus
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US Patent 7870520 Semiconductor device and yield calculation method
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US Patent 7870528 Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation
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US Patent 7870531 System for using partitioned masks to build a chip
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US Patent 7870532 Lithography simulation method, method of manufacturing a semiconductor device and program
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US Patent 7870533 Delay analysis apparatus, delay analysis method and computer product
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US Patent 7873931 Congestion-based routing with reconfigurable cross-points for dense signal tapping
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US Patent 7873935 Method of manufacturing a mask
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US Patent 7877716 Computer program products for determining stopping powers of design structures with respect to a traveling particle
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US Patent 7877721 Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits
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US Patent 7882456 Optical lithography correction process
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US Patent 7882458 Power consumption analyzing method and computer-readable storage medium
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US Patent 7882468 Integrated circuit device evaluation device, evaluation method, and evaluation program
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US Patent 7882472 Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process
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US Patent 7882478 Spacers for reducing crosstalk and maintaining clearances
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US Patent 7882483 Method for checking constraints equivalence of an integrated circuit design
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US Patent 7886241 System and method for automated electronic device design
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US Patent 7886250 Reconfigurable integrated circuit
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US Patent 7886252 Same subgraph detector for data flow graph, high-order combiner, same subgraph detecting method for data flow graph, same subgraph detection control program for data flow graph, and readable recording medium
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US Patent 7890899 Variable clocked scan test improvements
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US Patent 7890901 Method and system for verifying the equivalence of digital circuits
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US Patent 7895539 System for improving a logic circuit and associated methods
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US Patent 7895543 Method for verifying timing of a circuit with RLC inputs and outputs
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US Patent 7900172 Method and apparatus for analyzing power consumption
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US Patent 7900173 Temporal decomposition for design and verification
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US Patent 7900175 Method for verifying timing of a multi-phase, multi-frequency and multi-cycle circuit
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US Patent 7900177 Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
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US Patent 7900178 Integrated circuit (IC) design method, system and program product
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US Patent 7900183 Vendor independent method to merge coverage results for different designs
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US Patent 7904854 System and method for checking for sub-resolution assist features
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US Patent 7904858 Logic synthesis apparatus
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US Patent 7904863 Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
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US Patent 7904872 System-on-chip (SOC), design structure and method
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US Patent 7904873 System-on-chip (SOC), design structure and method
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US Patent 7913219 Orientation optimization method of 2-pin logic cell
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US Patent 7913221 Interconnect structure of semiconductor integrated circuit, and design method and device therefor
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US Patent 7926005 Pattern-driven routing
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US Patent 7930663 Structure for integrated circuit for measuring set-up and hold times for a latch element
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US Patent 7934173 Reverse dummy insertion algorithm
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US Patent 7934175 Parameter adjustment method, semiconductor device manufacturing method, and recording medium
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US Patent 7934183 Method and apparatus for simulating behavioral constructs using indeterminate values
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US Patent 7934188 Legalization of VLSI circuit placement with blockages using hierarchical row slicing
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US Patent 7937675 Structure including transistor having gate and body in direct self-aligned contact
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US Patent 7937677 Design-for-test-aware hierarchical design planning
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US Patent 7937681 Method and mechanism for implementing automated PCB routing
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US Patent 7941768 Photolithographic process simulation in integrated circuit design and manufacturing
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US Patent 7941778 System and method of determining minimum cost path
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US Patent 7941780 Intersect area based ground rule for semiconductor design
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US Patent 7945876 Method and apparatus for automatic synthesis of an electronic circuit model
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US Patent 7945883 Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design
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US Patent 7945885 Power managers for an integrated circuit
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US Patent 7949970 Fast reduction of system models
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US Patent 7949979 Predicting induced crosstalk for the pins of a programmable logic device
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US Patent 7949985 Method for compensation of process-induced performance variation in a MOSFET integrated circuit
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US Patent 7949989 Methods, systems and computer program products for layout device matching driven by a schematic editor
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US Patent 7958468 Unidirectional relabeling for subcircuit recognition
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US Patent 7958471 Structure for couple noise characterization using a single oscillator
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US Patent 7958481 Method of designing a semiconductor integrated circuit having a dummy area and the semiconductor integrated circuit thereof
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US Patent 7958482 Stitched circuitry region boundary identification for stitched IC chip layout
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US Patent 7966597 Method and system for routing of integrated circuit design
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US Patent 7971168 Method for repeated block timing analysis
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US Patent 7971171 Method and system for electromigration analysis on signal wiring
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US Patent 7979823 Identification of voltage reference errors in PCB designs
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US Patent 7979824 Cost-benefit optimization for an airgapped integrated circuit
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US Patent 7984413 Wiring design processing method and wiring design processing apparatus
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US Patent 7987438 Structure for initializing expansion adapters installed in a computer system having similar expansion adapters
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US Patent 7992116 Method for verifying timing of a circuit
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US Patent 7992119 Real-time background legality verification of pin placement
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US Patent 7996801 Methods and systems for on-the-fly chip verification
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US Patent 7996809 Software controlled transistor body bias
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US Patent 7996811 Power managers for an integrated circuit
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US Patent 8001513 Integrated circuit apparatus, systems, and methods
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US Patent 8006211 IC chip and design structure including stitched circuitry region boundary identification
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US Patent 8006216 Dynamic push for topological routing of semiconductor packages
Edits on 8 Dec, 2021
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edited on 8 Dec, 2021
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US Patent 8006216 Dynamic push for topological routing of semiconductor packages
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edited on 8 Dec, 2021
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US Patent 8006211 IC chip and design structure including stitched circuitry region boundary identification
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Golden AI
edited on 8 Dec, 2021
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US Patent 8001513 Integrated circuit apparatus, systems, and methods
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edited on 8 Dec, 2021
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US Patent 7996809 Software controlled transistor body bias
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US Patent 7996811 Power managers for an integrated circuit
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US Patent 7996801 Methods and systems for on-the-fly chip verification
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Golden AI
edited on 8 Dec, 2021
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US Patent 7992119 Real-time background legality verification of pin placement
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US Patent 7992116 Method for verifying timing of a circuit
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US Patent 7984413 Wiring design processing method and wiring design processing apparatus
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Golden AI
edited on 8 Dec, 2021
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US Patent 7979824 Cost-benefit optimization for an airgapped integrated circuit
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edited on 8 Dec, 2021
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US Patent 7979823 Identification of voltage reference errors in PCB designs
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edited on 8 Dec, 2021
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US Patent 7971171 Method and system for electromigration analysis on signal wiring
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edited on 8 Dec, 2021
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US Patent 7971168 Method for repeated block timing analysis
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edited on 8 Dec, 2021
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US Patent 7966597 Method and system for routing of integrated circuit design
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edited on 7 Dec, 2021
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US Patent 7958468 Unidirectional relabeling for subcircuit recognition
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edited on 7 Dec, 2021
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US Patent 7958482 Stitched circuitry region boundary identification for stitched IC chip layout
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edited on 7 Dec, 2021
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US Patent 7958471 Structure for couple noise characterization using a single oscillator

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