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Matthew S. Smith

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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7163864 Method of fabricating semiconductor side wall fin
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US Patent 7220666 Interconnection element for BGA housings and method for producing the same
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US Patent 7364992 Method of forming polycrystalline silicon thin film and method of manufacturing thin film transistor using the method
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US Patent 7375011 Ex-situ doped semiconductor transport layer
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US Patent 7381628 Process of making a microtube and microfluidic devices formed therewith
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US Patent 7384858 Wafer dividing method
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US Patent 7387971 Fabricating method for flat panel display device
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US Patent 7391063 Display device
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US Patent 7391122 Techniques for flip chip package migration
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US Patent 7393714 Method of manufacturing external force detection sensor
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US Patent 7394113 Self-alignment scheme for a heterojunction bipolar transistor
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US Patent 7394151 Semiconductor package with plated connection
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US Patent 7396738 Method of forming isolation structure of flash memory device
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US Patent 7399675 Electronic device including an array and process for forming the same
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US Patent 7399694 Semiconductor device and a manufacturing method of the same
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US Patent 7405095 Method for producing color-wheel segments
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US Patent 7407822 Method for inspecting insulating film for film carrier tape for mounting electronic components thereon, inspection apparatus for inspecting the insulating film, punching apparatus for punching the insulating film, and method for controlling the punching apparatus
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US Patent 7407893 Liquid precursors for the CVD deposition of amorphous carbon films
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US Patent 7410874 Method of integrating triple gate oxide thickness
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US Patent 7410917 Atomic layer deposited Zr-Sn-Ti-O films using TiI
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US Patent 7413924 Plasma etch process for defining catalyst pads on nanoemissive displays
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US Patent 7413985 Method for forming a self-aligned nitrogen-containing copper silicide capping layer in a microstructure device
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US Patent 7416931 Methods for fabricating a stress enhanced MOS circuit
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US Patent 7419882 Alignment mark and alignment method for the fabrication of trench-capacitor dram devices
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US Patent 7427518 Semiconductor device fabrication method and fabrication apparatus
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US Patent 7429507 Semiconductor device having both memory and logic circuit and its manufacture
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US Patent 7432125 CMOS image sensor and manufacturing method thereof
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US Patent 7432564 Pixel structure
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US Patent 7432601 Semiconductor package and fabrication process thereof
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US Patent 7435649 Floating-gate non-volatile memory and method of fabricating the same
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US Patent 7439089 Method of fabricating array substrate having color filter on thin film transistor structure
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US Patent 7439091 Light-emitting diode and method for manufacturing the same
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US Patent 7439109 Method of forming an integrated circuit structure on a hybrid crystal oriented substrate
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US Patent 7439134 Method for process integration of non-volatile memory cell transistors with transistors of another type
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US Patent 7442601 Stress enhanced CMOS circuits and methods for their fabrication
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US Patent 7446000 Method of fabricating semiconductor device having gate dielectrics with different thicknesses
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US Patent 7446030 Methods for fabricating current-carrying structures using voltage switchable dielectric materials
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US Patent 7446394 Semiconductor device fabricated by selective epitaxial growth method
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US Patent 7449367 Adhesive film for semiconductor, metal sheet with such adhesive film, wiring substrate with adhesive film, semiconductor device, and method for manufacturing semiconductor device
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US Patent 7452749 Method for manufacturing flip-chip type semiconductor device featuring nickel electrode pads, and plating apparatus used in such method
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US Patent 7452811 Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same
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US Patent 7453106 Semiconductor device with stress reducing trench fill containing semiconductor microparticles in shallow trench isolation
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US Patent 7456076 Techniques for forming passive devices during semiconductor back-end processing
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US Patent 7456496 Package design and method of manufacture for chip grid array
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US Patent 7459364 Methods of forming self-aligned floating gates using multi-etching
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US Patent 7462538 Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials
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US Patent 7465674 Manufacturing method of semiconductor device
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US Patent 7468320 Reduced electromigration and stressed induced migration of copper wires by surface coating
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US Patent 7491586 Semiconductor device with leakage implant and method of fabrication
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US Patent 7495267 Semiconductor structure having a strained region and a method of fabricating same
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US Patent 7498226 Method for fabricating semiconductor device with step gated asymmetric recess
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US Patent 7498658 Trench gate type insulated gate bipolar transistor
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US Patent 7504699 Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections
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US Patent 7521312 Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device
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US Patent 7566951 Silicon structures with improved resistance to radiation events
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US Patent 7573142 Alignment key structure in a semiconductor device and method of forming the same
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US Patent 7592259 Methods and systems for barrier layer surface passivation
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US Patent 7754535 Method of manufacturing chip integrated substrate
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US Patent 7795663 Acceptor doped barium titanate based thin film capacitors on metal foils and methods of making thereof
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US Patent 7804138 Buried guard ring and radiation hardened isolation structures and fabrication methods
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US Patent 7812378 Semiconductor device with high capacitance and low leakage current
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US Patent 7816160 Manufacturing method for semiconductor device
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US Patent 7816190 E-ink display and method for repairing the same
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US Patent 7824965 Near chip scale package integration process
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US Patent 7829387 Electronic apparatus and method of manufacturing the same
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US Patent 7829474 Method for arraying nano material and method for fabricating liquid crystal display device using the same
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US Patent 7833821 Method and apparatus for thin film solar cell manufacturing
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US Patent 7833891 Semiconductor device manufacturing method using oxygen diffusion barrier layer between buried oxide layer and high K dielectric layer
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US Patent 7834394 Semiconductor structure and method of fabricating the same
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US Patent 7838397 Process and system for laser annealing and laser-annealed semiconductor film
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US Patent 7838421 Method of forming metal line of semiconductor device
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US Patent 7838925 Integrated circuit including a vertical transistor and method
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US Patent 7842530 Method of manufacturing vertical cavity surface emitting laser and method of manufacturing laser array, vertical cavity surface emitting laser and laser array, and image forming apparatus with laser array
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US Patent 7842610 Semiconductor device
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US Patent 7846759 Multi-junction solar cells and methods of making same using layer transfer and bonding techniques
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US Patent 7846815 Eutectic flow containment in a semiconductor fabrication process
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US Patent 7851249 Tandem solar cell including an amorphous silicon carbide layer and a multi-crystalline silicon layer
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US Patent 7851256 Method of manufacturing chip-on-chip semiconductor device
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US Patent 7851310 Method for forming semiconductor device
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US Patent 7851315 Method for fabricating a field effect transistor having a dual thickness gate electrode
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US Patent 7851378 Method for growing Ge expitaxial layer on patterned structure with cyclic annealing
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US Patent 7851889 MOSFET device including a source with alternating P-type and N-type regions
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US Patent 7851891 Semiconductor device and method for fabricating the same
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US Patent 7851902 Resin-sealed semiconductor device, manufacturing method thereof, base material for the semiconductor device, and layered and resin-sealed semiconductor device
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US Patent 7855119 Method for forming polycrystalline thin film bipolar transistors
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US Patent 7855156 Method of and apparatus for inline deposition of materials on a non-planar surface
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US Patent 7855409 Flash memory device and method of fabricating the same
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US Patent 7858472 Scalable self-aligned dual floating gate memory cell array and methods of forming the array
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US Patent 7858499 Dicing tape and die attach adhesive with patterned backing
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US Patent 7858532 Dielectric layer structure and manufacturing method thereof
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US Patent 7859017 Normally-off field-effect semiconductor device
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US Patent 7863163 Epitaxial deposition of doped semiconductor materials
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US Patent 7863176 Low-resistance interconnects and methods of making same
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US Patent 7863177 Fuse in a semiconductor device and method for fabricating the same
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US Patent 7863676 Semiconductor devices and methods of fabricating the same
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US Patent 7863701 Optical semiconductor device and method for manufacturing the same
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US Patent 7867798 Semiconductor laser, method of manufacturing semiconductor laser, optical pickup and optical disk system
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US Patent 7867809 One-step diffusion method for fabricating a differential doped solar cell
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US Patent 7867830 Manufacturing method for electronic component with sealing film
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US Patent 7867881 Method of manufacturing nitride semiconductor substrate
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US Patent 7867898 Method forming ohmic contact layer and metal wiring in semiconductor device
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US Patent 7867921 Reduction of etch-rate drift in HDP processes
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US Patent 7867925 Method for manufacturing pattern formed structure
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US Patent 7868370 Single gate nonvolatile memory cell with transistor and capacitor
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US Patent 7872262 Pixel structure and manufacturing method thereof
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US Patent 7872310 Semiconductor structure and system for fabricating an integrated circuit chip
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US Patent 7872313 Semiconductor device having an expanded storage node contact and method for fabricating the same
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US Patent 7875469 Method of operating and process for fabricating an electron source
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US Patent 7875560 Semiconductor having optimized insulation structure and process for producing the semiconductor
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US Patent 7875945 Rear electrode structure for use in photovoltaic device such as CIGS/CIS photovoltaic device and method of making same
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US Patent 7879708 Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate
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US Patent 7879718 Local interconnect having increased misalignment tolerance
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US Patent 7879720 Methods of forming electrical interconnects using electroless plating techniques that inhibit void formation
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US Patent 7880261 Isolation technique allowing both very high and low voltage circuits to be fabricated on the same chip
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US Patent 7883945 Array substrate and method of manufacturing the same
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US Patent 7883967 Nonvolatile semiconductor memory device, semiconductor device and manufacturing method of nonvolatile semiconductor memory device
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US Patent 7884007 Super high density module with integrated wafer level packages
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US Patent 7884013 Dual damascene with via liner
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US Patent 7888189 Method for manufacturing electronic device
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US Patent 7888220 Self-aligned insulating etchstop layer on a metal contact
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US Patent 7888249 Use of chained implants in solar cell
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US Patent 7888252 Self-aligned contact
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US Patent 7888684 Light emitting device and method of producing light emitting device with a semiconductor includes one of chalcopyrite and oxychacogenide
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US Patent 7892858 Semiconductor package with stacked semiconductor die each having IPD and method of reducing mutual inductive coupling by providing selectable vertical and lateral separation between IPD
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US Patent 7892895 Diode junction poly fuse
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US Patent 7892910 Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration
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US Patent 7892944 Method of forming transistor in semiconductor device
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US Patent 7892975 Method for selectively forming electric conductor and method for manufacturing semiconductor device
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US Patent 7897430 Organic thin film transistors including metal oxide nanoparticles within a photocurable transparent polymer gate insulator layer and method for fabricating the same by using sol-gel and photocuring reactions
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US Patent 7897435 Re-assembly process for MEMS structures
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US Patent 7897488 Dividing method for wafer having film on the front side thereof
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US Patent 7897493 Inducement of strain in a semiconductor layer
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US Patent 7897504 Method for fabricating semiconductor device
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US Patent 7897513 Method for forming a metal silicide
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US Patent 7897522 Method and system for improving particle beam lithography
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US Patent 7897524 Manufacturing method for semiconductor device and manufacturing apparatus for semiconductor device
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US Patent 7901958 Fabrication method of semiconductor integrated circuit device
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US Patent 7901976 Method of forming borderless contacts
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US Patent 7902037 Isolation structure in memory device and method for fabricating the same
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US Patent 7902063 Methods for discretized formation of masking and capping layers on a substrate
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US Patent 7902070 Method and system for producing optically transparent noble metal films
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US Patent 7902078 Processing method and plasma etching method
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US Patent 7902580 Assemblies comprising magnetic elements and magnetic barrier or shielding
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US Patent 7906836 Heat spreader structures in scribe lines
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US Patent 7910404 Method of manufacturing a stacked die module
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US Patent 7910423 Semiconductor device and method of manufacturing the same
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US Patent 7910441 Multi-gate semiconductor device and method for forming the same
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US Patent 7910465 Manufacturing method of semiconductor substrate
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US Patent 7910496 Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines
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US Patent 7911030 Resistive memory device and method of fabricating the same
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US Patent 7911055 Semiconductor device and manufacturing method of the same
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US Patent 7915059 Method for fabricating organic light emitting diode with fluorine-ion-doped electrode
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US Patent 7915706 Linearity improvements of semiconductor substrate using passivation
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US Patent 7915714 Semiconductor light emitting element and wafer
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US Patent 7919340 Method for manufacturing light-emitting device
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US Patent 7919353 Semiconductor device and manufacturing method thereof
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US Patent 7919385 Semiconductor device and method of forming the same
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US Patent 7919409 Materials for adhesion enhancement of copper film on diffusion barriers
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US Patent 7919808 Flash memory device
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US Patent 7923295 Semiconductor device and method of forming the device using sacrificial carrier
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US Patent 7923296 Board on chip package and method of manufacturing the same
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US Patent 7923307 Semiconductor device with fuse and method for fabricating the same
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US Patent 7923362 Method for manufacturing a metal-semiconductor contact in semiconductor components
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US Patent 7923821 Semiconductor integrated circuit substrate containing isolation structures
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US Patent 7927937 Fabrication of large grain polycrystalline silicon film by nano aluminum-induced crystallization of amorphous silicon
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US Patent 7927965 Method for fabricating partial SOI substrate
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US Patent 7928005 Method for forming narrow structures in a semiconductor device
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US Patent 7928014 Method for manufacturing a semiconductor device including a silicon film
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US Patent 7928577 Interconnect structures for integration of multi-layered integrated circuit devices and methods for forming the same
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US Patent 7932109 Organic electroluminescent display and manufacturing method therefor
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US Patent 7932113 Method of fabricating organic light emitting diode display
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US Patent 7932137 Thin film transistor and manufacturing method of the same
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US Patent 7932145 Method of forming a bipolar transistor and semiconductor component thereof
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US Patent 7932150 Lateral oxidation with high-K dielectric liner
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US Patent 7932159 Flash memory device and method of fabricating the same
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US Patent 7932166 Field effect transistor having a stressed contact etch stop layer with reduced conformality
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US Patent 7932535 Synthetic jet cooling system for LED module
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US Patent 7935558 Sodium salt containing CIG targets, methods of making and methods of use thereof
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US Patent 7935593 Stress optimization in dual embedded epitaxially grown semiconductor processing
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US Patent 7935608 Storage cell having a T-shaped gate electrode and method for manufacturing the same
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US Patent 7935988 Method of manufacturing solid state imaging device, solid state imaging device, and camera using solid state imaging device
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US Patent 7939379 Hybrid carrier and a method for making the same
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US Patent 7939411 Method for fabricating semiconductor device with vertical gate
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US Patent 7939422 Methods of thin film process
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US Patent 7939441 P-type silicon wafer and method for heat-treating the same
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US Patent 7943437 Apparatus and method for electronic fuse with improved ESD tolerance
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US Patent 7943440 Fabrication method of thin film device
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US Patent 7947520 Semiconductor laser and method of making the same
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US Patent 7947566 Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate
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US Patent 7947567 Method of fabricating a semiconductor device with reduced oxide film variation
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US Patent 7947570 Manufacturing method and manufacturing apparatus of semiconductor substrate
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US Patent 7947612 Electronic device array
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US Patent 7947979 Semiconductor device
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US Patent 7948010 Dual seed semiconductor photodetectors
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US Patent 7948031 Semiconductor device and method of fabricating semiconductor device
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US Patent 7951691 Method for producing a thin semiconductor chip comprising an integrated circuit
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US Patent 7951720 Method of forming a contact hole for a semiconductor device
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US Patent 7952165 Heterojunction bipolar transistor (HBT) with self-aligned sub-lithographic metal-semiconductor alloy base contacts
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US Patent 7955960 Nonvolatile memory device and method of fabricating the same
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US Patent 7955961 Process for manufacture of trench Schottky
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US Patent 7956360 Growth of planar reduced dislocation density M-plane gallium nitride by hydride vapor phase epitaxy
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US Patent 7960226 Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness
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US Patent 7960235 Method for manufacturing a MOSFET with a surrounding gate of bulk Si
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US Patent 7960247 Die thinning processes and structures
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US Patent 7960261 Method for manufacturing crystalline semiconductor film and method for manufacturing thin film transistor
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US Patent 7964417 Method of measuring degree of crystallinity of polycrystalline silicon substrate, method of fabricating organic light emitting display using the same, and organic light emitting display fabricated using the same
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US Patent 7964462 Method of manufacturing semiconductor device
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US Patent 7964471 Methods of forming capacitors
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US Patent 7964474 Use of field oxidation to simplify chamber fabrication in microfluidic devices
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US Patent 7964490 Methods of forming nickel sulfide film on a semiconductor device
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US Patent 7964893 Forming ESD diodes and BJTs using FinFET compatible processes
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US Patent 7964928 Photodetector with an improved resolution
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US Patent 7968386 Method for manufacturing thin film integrated circuit, and element substrate
Edits on 8 Dec, 2021
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edited on 8 Dec, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 7968386 Method for manufacturing thin film integrated circuit, and element substrate
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7964928 Photodetector with an improved resolution
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7964893 Forming ESD diodes and BJTs using FinFET compatible processes
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7964490 Methods of forming nickel sulfide film on a semiconductor device
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Golden AI
edited on 8 Dec, 2021
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Infobox
Patent primary examiner of
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US Patent 7964471 Methods of forming capacitors
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edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7964462 Method of manufacturing semiconductor device
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7964474 Use of field oxidation to simplify chamber fabrication in microfluidic devices
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Golden AI
edited on 8 Dec, 2021
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edited on 7 Dec, 2021
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edited on 7 Dec, 2021
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Patent primary examiner of
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US Patent 7960247 Die thinning processes and structures
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edited on 7 Dec, 2021
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
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Patent primary examiner of
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US Patent 7960235 Method for manufacturing a MOSFET with a surrounding gate of bulk Si
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Golden AI
edited on 7 Dec, 2021
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Golden AI
edited on 7 Dec, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 7955961 Process for manufacture of trench Schottky
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7955960 Nonvolatile memory device and method of fabricating the same
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Golden AI
edited on 7 Dec, 2021
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
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Patent primary examiner of
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US Patent 7951720 Method of forming a contact hole for a semiconductor device
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Golden AI
edited on 7 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7951691 Method for producing a thin semiconductor chip comprising an integrated circuit
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Golden AI
edited on 7 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7948010 Dual seed semiconductor photodetectors

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