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US Patent 7089517 Method for design validation of complex IC
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US Patent 7089520 Methodology for placement based on circuit function and latchup sensitivity
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US Patent 7089521 Method for legalizing the placement of cells in an integrated circuit layout
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US Patent 7089522 Device, design and method for a slot in a conductive area
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US Patent 7093205 Method and apparatus for efficient semiconductor process evaluation
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US Patent 7093209 Method and apparatus for packaging test integrated circuits
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US Patent 7093217 Method and apparatus for determining the optimal fanout across a logic element
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US Patent 7093221 Method and apparatus for identifying a group of routes for a set of nets
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US Patent 7093225 FPGA with hybrid interconnect
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US Patent 7093227 Methods of forming patterned reticles
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US Patent 7093229 System and method for providing defect printability analysis of photolithographic masks with job-based automation
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US Patent 7096434 Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs
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US Patent 7096438 Method of using clock cycle-time in determining loop schedules during circuit design
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US Patent 7096444 Representing device layout using tree structure
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US Patent 7100125 Aggressor classification method for analyzing crosstalk of circuit
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US Patent 7100127 Impedance matching circuit design method
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US Patent 7100134 Method and platform for integrated physical verifications and manufacturing enhancements
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US Patent 7100143 Method and apparatus for pre-tabulating sub-networks
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US Patent 7103858 Process and apparatus for characterizing intellectual property for integration into an IC platform environment
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US Patent 7103865 Process and apparatus for placement of megacells in ICs design
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US Patent 7103870 Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI
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US Patent 7107551 Optimization of circuit designs using a continuous spectrum of library cells
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US Patent 7107554 Line width check in layout database
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US Patent 7107560 Method and apparatus for designing custom programmable logic devices
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US Patent 7107563 Integrated circuit signal routing using resource cost assignment and costing data
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US Patent 7107571 Visual analysis and verification system using advanced tools
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US Patent 7107572 Methods of forming patterned reticles
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US Patent 7111258 Method for designing logic circuit and CAD program
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US Patent 7111259 Crosstalk mitigation method and system
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US Patent 7111261 Method of determining library parameters using timing surface planarity
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US Patent 7111263 Process for designing and manufacturing semi-conductor memory components, in particular DRAM components
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US Patent 7114144 Mask pattern inspecting method, inspection apparatus, inspecting data used therein and inspecting data generating method
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US Patent 7117457 Current scheduling system and method for optimizing multi-threshold CMOS designs
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US Patent 7117464 System and method for evaluating signal coupling between differential traces in a package design
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US Patent 7117473 System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocks
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US Patent 7117476 Determining feasibility of IC edits
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US Patent 7124383 Integrated proof flow system and method
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US Patent 7124385 Method for automated transistor folding
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US Patent 7124390 Generating a split power plane of a multi-layer printed circuit board
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US Patent 7124396 Alternating phase-shift mask rule compliant IC design
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US Patent 7127699 Method for optimizing a number of kernels used in a sum of coherent sources for optical proximity correction in an optical microlithography process
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US Patent 7131075 Semiconductor device having intrinsic precision properties
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US Patent 7134112 Incremental routing in integrated circuit design
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US Patent 11176299 Analysis of signal transitions in feedback circuits
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US Patent 11176305 Method and system for sigma-based timing optimization
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US Patent 11177668 Managing top-off charging and discharge testing of battery packs to optimize capacity
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US Patent 7137079 Memory compiler with ultra low power feature and method of use
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US Patent 7137083 Verification of integrated circuit tests using test simulation and integrated circuit simulation with simulated failure
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US Patent 7137091 Hierarchical repeater insertion
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US Patent 7139991 Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs
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US Patent 7143369 Design partitioning for co-stimulation
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US Patent 7143378 Method and apparatus for timing characterization of integrated circuit designs
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US Patent 7143384 Methods of routing programmable logic devices to minimize programming time
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US Patent 7143386 Type configurable memory methodology for use with metal programmable devices
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US Patent 7146582 Logic circuit optimizing method, logic circuit optimizing device and logic circuit composing device
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US Patent 7146587 Scalable logic self-test configuration for multiple chips
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US Patent 7146591 Method of selecting cells in logic restructuring
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US Patent 7146594 System, method, and computer program product for schematic generation
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US Patent 7146595 Data structures for representing the logical and physical information of an integrated circuit
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US Patent 7149992 Method for faster timing closure and better quality of results in IC physical design
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US Patent 7149994 Integrated clock and input output placer
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US Patent 7149996 Reconfigurable multi-stage crossbar
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US Patent 7149998 Lithography process modeling of asymmetric patterns
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US Patent 7152214 Recognition of a state machine in high-level integrated circuit description language code
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US Patent 7155687 Methods and apparatus for scan insertion
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US Patent 7155697 Routing method and apparatus
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US Patent 7159195 Reduction of storage elements in synthesized synchronous circuits
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US Patent 7159198 System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit model
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US Patent 7159204 System and method for design entry and synthesis in programmable logic devices
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US Patent 7165234 Model-based data conversion
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US Patent 7171635 Method and apparatus for routing
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US Patent 7171636 Pass-transistor logic circuit and a method of designing thereof
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US Patent 7171642 Method and system for creating a netlist allowing current measurement through a sub-circuit
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US Patent 7174519 Vector Logic techniques for multilevel minimization
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US Patent 7174523 Variable sigma adjust methodology for static timing
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US Patent 7178128 Alternating phase shift mask design conflict resolution
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US Patent 7181705 Hierarchical test circuit structure for chips with multiple circuit blocks
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US Patent 7185298 Method of parasitic extraction from a previously calculated capacitance solution
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US Patent 7185301 Generic method and apparatus for implementing source synchronous interface in platform ASIC
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US Patent 7185306 Method and apparatus for enhancing signal routability
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US Patent 7185307 Method of fabricating and integrated circuit through utilizing metal layers to program randomly positioned basic units
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US Patent 7185312 Exposure method for correcting line width variation in a photomask
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US Patent 7188328 Method for finding maximum volume and minimum cut in a network of interconnected nodes
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US Patent 7191422 System and method for determining a carrier layout using cornered chip-to-chip input/output
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US Patent 7194709 Automatic alignment of integrated circuit and design layout of integrated circuit to more accurately assess the impact of anomalies
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US Patent 7194712 Method and apparatus for identifying line-end features for lithography verification
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US Patent 7194715 Method and system for performing static timing analysis on digital electronic circuits
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US Patent 7194720 Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices
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US Patent 7197721 Weight compression/decompression system
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US Patent 7197727 Interconnect speed sensing circuitry
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US Patent 7197731 Virtual component having a detachable verification-supporting circuit, a method of verifying the same, and a method of manufacturing an integrated circuit
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US Patent 7200821 Receiver and method for mitigating temporary logic transitions
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US Patent 7200826 RRAM memory timing learning tool
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US Patent 7200828 Automatic placement and routing apparatus and automatic placement and routing method
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US Patent 7203921 Method and system for designing an integrated circuit with reduced noise
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US Patent 7203922 Merging of infrastructure within a development environment
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US Patent 7207016 Method for classifying errors in the layout of a semiconductor circuit
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US Patent 7207024 Automatic insertion of clocked elements into an electronic design to improve system performance
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US Patent 7207030 Method for improving a simulation model of photolithographic projection
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US Patent 7210110 Method for determining a matched routing arrangement for semiconductor devices
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US Patent 7213226 Pattern dimension correction method and verification method using OPC, mask and semiconductor device fabricated by using the correction method, and system and software product for executing the correction method
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US Patent 7216311 System and method for evaluating a semiconductor device pattern, method for controlling process of forming a semiconductor device pattern and method for monitoring a semiconductor device manufacturing process
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US Patent 7216316 Method for evaluating nets in crosstalk noise analysis
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US Patent 7222325 Method for modifying an integrated circuit
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US Patent 7225415 Vector logic techniques for multilevel minimization with multiple outputs
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US Patent 7225417 Method and system to verify a circuit design by verifying consistency between two different language representations of a circuit design
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US Patent 7231615 Methods and apparatus for transforming sequential logic designs into equivalent combinational logic
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US Patent 7231621 Speed verification of an embedded processor in a programmable logic device
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US Patent 7231629 Feature optimization using enhanced interference mapping lithography
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US Patent 7234130 Long range corrections in integrated circuit layout designs
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US Patent 7237210 Methods, systems and media for managing functional verification of a parameterizable design
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US Patent 7237215 Method for providing memory cells capable of allowing multiple variations of metal level assignments for bitlines and wordlines
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US Patent 7237217 Resonant tree driven clock distribution grid
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US Patent 7240311 Combinational equivalence checking methods and systems with internal don't cares
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US Patent 7240322 Method of adding fabrication monitors to integrated circuit chips
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US Patent 7243312 Method and apparatus for power optimization during an integrated circuit design process
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US Patent 7243317 Parameter checking method for on-chip ESD protection circuit physical design layout verification
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US Patent 7251791 Methods to generate state space models by closed forms and transfer functions by recursive algorithms for RLC interconnect and transmission line and their model reduction and simulations
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US Patent 7251794 Simulation testing of digital logic circuit designs
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US Patent 7251796 Predictive event scheduling in an iterative tran resolution network
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US Patent 7251799 Metal interconnect structure for integrated circuits and a design rule therefor
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US Patent 7251804 Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof
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US Patent 7251805 ASICs having more features than generally usable at one time and methods of use
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US Patent 7254804 Method of verifying corrected photomask-pattern results and device for the same
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US Patent 7257779 Sea-of-cells array of transistors
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US Patent 7257780 Software-to-hardware compiler
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US Patent 7257783 Technology migration for integrated circuits with radical design restrictions
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US Patent 7260793 Apparatus and method for test-stimuli compaction
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US Patent 7260799 Exploiting suspected redundancy for enhanced design verification
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US Patent 7260802 Method and apparatus for partitioning an integrated circuit chip
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US Patent 7263677 Method and apparatus for creating efficient vias between metal layers in semiconductor designs and layouts
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US Patent 7266792 Automated noise convergence for cell-based integrated circuit design
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US Patent 7266794 Apparatus for and method of analyzing transmission characteristics of a circuit apparatus
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US Patent 7272805 System and method for converting a flat netlist into a hierarchical netlist
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US Patent 7272806 System and method for evaluating power and ground vias in a package design
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US Patent 7272809 Method, apparatus and computer program product for implementing enhanced high frequency return current paths utilizing decoupling capacitors in a package design
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US Patent 7284215 Method to solve similar timing paths
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US Patent 7284231 Layout modification using multilayer-based constraints
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US Patent 7290224 Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit
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US Patent 7290225 Method for compressing semiconductor integrated circuit, using design region divided into plural blocks
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US Patent 7290230 System and method for verifying a digital design using dynamic abstraction
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US Patent 7290236 Configuration and/or reconfiguration of integrated circuit devices that include programmable logic and microprocessor circuitry
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US Patent 7296254 System and method for using MPW integration service on demand
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US Patent 7299434 Slack value setting method, slack value setting device, and recording medium recording a computer-readable slack value setting program
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US Patent 7299435 Frequency dependent timing margin
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US Patent 7302654 Method of automating place and route corrections for an integrated circuit design from physical design validation
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US Patent 7302658 Methods for evaluating quality of test sequences for delay faults and related technology
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US Patent 7302664 System and method for automatic insertion of on-chip decoupling capacitors
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US Patent 7302667 Methods and apparatus for generating programmable device layout information
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US Patent 7305634 Method to selectively identify at risk die based on location within the reticle
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US Patent 7305640 Programmable soft macro memory using gate array base cells
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US Patent 7305646 Relocatable mixed-signal functions
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US Patent 7308655 Method and system for alerting an entity to design changes impacting the manufacture of a semiconductor device in a virtual fab environment
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US Patent 7308660 Calculation system of fault coverage and calculation method of the same
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US Patent 7310792 Method and system for modeling variation of circuit parameters in delay calculation for timing analysis
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US Patent 7313778 Method system and apparatus for floorplanning programmable logic designs
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US Patent 7315990 Method and system for creating, viewing, editing, and sharing output from a design checking system
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US Patent 7320117 Design method for semiconductor integrated circuit device using path isolation
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US Patent 7325208 Method, apparatus and system for inductance modeling in an electrical configuration
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US Patent 7328422 Design support apparatus, design support program and design support method for supporting design of semiconductor integrated circuit
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US Patent 7328423 Method for evaluating logic functions by logic circuits having optimized number of and/or switches
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US Patent 7334207 Automatic placement based ESD protection insertion
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US Patent 7334212 Method for interlayer and yield based optical proximity correction
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US Patent 7340712 System and method for creating a standard cell library for reduced leakage and improved performance
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US Patent 7343572 Vector interface to shared memory in simulating a circuit design
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US Patent 7346865 Fast evaluation of average critical area for IC layouts
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US Patent 7346880 Differential clock ganging
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US Patent 7346887 Method for fabricating integrated circuit features
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US Patent 7350166 Method and system for reversing the effects of sequential reparameterization on traces
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US Patent 7350182 Methods of forming patterned reticles
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US Patent 7353469 Method and program for designing semiconductor device
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US Patent 7353484 Methods and apparatus for variable latency support
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US Patent 7356791 Method and apparatus for rapid electromagnetic analysis
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US Patent 7356799 Timing exact design conversions from FPGA to ASIC
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US Patent 7360185 Design verification using sequential and combinational transformations
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US Patent 7363595 Method and apparatus for analog compensation of driver output signal slew rate against device impedance variation
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US Patent 7363610 Building integrated circuits using a common database
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US Patent 11180049 Mobile modular battery charging and exchange system
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US Patent 7367006 Hierarchical, rules-based, general property visualization and editing method and system
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US Patent 7370291 Method for mapping logic design memory into physical memory devices of a programmable logic device
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US Patent 7370292 Method for incremental design reduction via iterative overapproximation and re-encoding strategies
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US Patent 7370293 Integrated circuit design system, integrated circuit design program, and integrated circuit design method
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US Patent 7370295 Directed design space exploration
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US Patent 7370309 Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraints
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US Patent 7376919 Methods and apparatuses for automated circuit optimization and verification
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US Patent 7380223 Method and system for converting netlist of integrated circuit between libraries
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US Patent 7380230 Timing skew measurement system
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US Patent 7383523 Semiconductor integrated circuit
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US Patent 7383529 Method and apparatus for designing circuits using high-level synthesis
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US Patent 7386815 Test yield estimate for semiconductor products created from a library
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US Patent 7386822 Simultaneous timing-driven floorplanning and placement for heterogeneous field programmable gate array
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US Patent 7389478 System and method for designing a low leakage monotonic CMOS logic circuit
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US Patent 7389485 Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures
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US Patent 7389489 Techniques for editing circuit design files to be compatible with a new programmable IC
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US Patent 7392490 System and method of modelling capacitance of on-chip coplanar transmission line structures over a substrate
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US Patent 7392491 Systems and methods for operating an electromagnetic actuator
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US Patent 7392496 Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit
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US Patent 7392499 Placement of input/output blocks of an electronic design in an integrated circuit
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US Patent 7395517 Data aligner in reconfigurable computing environment
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US Patent 7398486 Method and apparatus for performing logical transformations for global routing
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US Patent 7398489 Advanced standard cell power connection
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US Patent 7398490 Digital circuit layout techniques using binary decision diagram for identification of input equivalence
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US Patent 7398500 Netlist synthesis and automatic generation of PC board schematics
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US Patent 7398501 System and method for optimizing an integrated circuit design
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US Patent 7401303 Method and apparatus for minimizing weighted networks with link and node labels
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US Patent 7404154 Basic cell architecture for structured application-specific integrated circuits
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US Patent 7404158 Inspection method and inspection apparatus for semiconductor integrated circuit
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US Patent 7406674 Method and apparatus for generating microcontroller configuration information
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US Patent 7409649 System and method for automatically calculating parameters of an MOSFET
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US Patent 7409655 Method of designing semiconductor integrated circuit and apparatus for designing the same
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US Patent 7415684 Facilitating structural coverage of a design during design verification
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US Patent 7415694 Graph based phase shift lithography mapping method and apparatus
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US Patent 7418680 Method and system to check correspondence between different representations of a circuit
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US Patent 7418681 Simulation system, simulation method and simulation program for verifying logic behavior of a semiconductor integrated circuit
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US Patent 7418693 System and method for analysis and transformation of layouts using situations
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US Patent 7424698 Allocation of combined or separate data and control planes
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US Patent 7424699 Modifying sub-resolution assist features according to rule-based and model-based techniques
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US Patent 7428712 Design optimization using approximate reachability analysis
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US Patent 7434186 Method and system for calculating high frequency limit capacitance and inductance for coplanar on-chip structure
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US Patent 7437689 Interconnect model-order reduction method
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US Patent 7437699 Layout method for semiconductor integrated circuit, layout program for semiconductor integrated circuit and layout system for semiconductor integrated circuit
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US Patent 7437702 Method for making mask in process of fabricating semiconductor device
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US Patent 7441220 Local preferred direction architecture, tools, and apparatus
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US Patent 7441222 Differential pair connection arrangement, and method and computer program product for making same
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US Patent 7448017 System and method of automatically generating kerf design data
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US Patent 7451415 Method for predicting inductance and self-resonant frequency of a spiral inductor
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US Patent 7454722 Acyclic modeling of combinational loops
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US Patent 7454726 Technique for generating input stimulus to cover properties not covered in random simulation
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US Patent 7454732 Methods and apparatuses for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs
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US Patent 7458045 Silicon tolerance specification using shapes as design intent markers
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US Patent 7458054 Method for designing integrated circuit package and method for manufacturing same
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US Patent 7461362 Replacing circuit design elements with their equivalents
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US Patent 7467359 Decoder using a memory for storing state metrics implementing a decoder trellis
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US Patent 7467360 LSI design support apparatus and LSI design support method
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US Patent 7472358 Method and system for outputting a sequence of commands and data described by a flowchart
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US Patent 7475375 Layout structure allowing independent supply of substrate/power supply potential of standard cell
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US Patent 7478350 Model modification method for timing Interoperability for simulating hardware
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US Patent 7478358 Semiconductor integrated circuit device
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US Patent 7480886 VLSI timing optimization with interleaved buffer insertion and wire sizing stages
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US Patent 7484187 Clock-gating through data independent logic
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US Patent 7487474 Designing an integrated circuit to improve yield using a variant design element
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US Patent 7487486 Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations
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US Patent 7493577 Automatic recognition of geometric points in a target IC design for OPC mask quality calculation
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US Patent 7493586 Method and system product for implementing uncertainty in integrated circuit designs with programmable logic
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US Patent 7496861 Method for generalizing design attributes in a design capture environment
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US Patent 7496870 Method of selecting cells in logic restructuring
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US Patent 7496876 Method for generating integrated functional testcases for multiple boolean algorithms from a single generic testcase template
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US Patent 7496878 Automatic wiring method and apparatus for semiconductor package and automatic identifying method and apparatus for semiconductor package
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US Patent 7496880 Method and apparatus for assessing the quality of a process model
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US Patent 7503019 Point and click expression builder
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US Patent 7503021 Integrated circuit diagnosing method, system, and program product
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US Patent 7503022 Test method for unit re-modification
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US Patent 7503029 Identifying layout regions susceptible to fabrication issues by using range patterns
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US Patent 7506278 Method and apparatus for improving multiplexer implementation on integrated circuits
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US Patent 7509600 Generating test patterns having enhanced coverage of untargeted defects
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US Patent 7509606 Method for optimizing power in a very large scale integration (VLSI) design by detecting clock gating opportunities
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US Patent 7509615 Circuit layout structure and method
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US Patent 7509616 Integrated circuit layout design system, and method thereof, and program
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US Patent 7509617 Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements
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US Patent 7509620 Dual phase shift photolithography masks for logic patterning
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US Patent 7509624 Method and apparatus for modifying a layout to improve manufacturing robustness
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US Patent 7512927 Printability verification by progressive modeling accuracy
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US Patent 7516424 Modeling and simulating a powergated hierarchical element
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US Patent 7516431 Methods and apparatus for validating design changes without propagating the changes throughout the design
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US Patent 11186180 Vehicle including remote terminals connected to battery so as to prevent electronic tampering
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US Patent 11188694 Dynamic simulation method of circulating temperature variation in RMR subsea pump mud-lift drilling system
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US Patent 7519925 Integrated circuit with dynamically controlled voltage supply
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US Patent 7519937 Circuit diagram processing system and method
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US Patent 7519941 Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry
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US Patent 7523421 Method and apparatus for reducing the cost of multiplexer circuitry
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US Patent 7523422 Method of fabricating an integrated circuit to improve soft error performance
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US Patent 7523423 Method and apparatus for production of data-flow-graphs by symbolic simulation
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US Patent 7523425 Test case generation algorithm for a model checker
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US Patent 7523427 Timing analyzer apparatus and timing analysis program recording medium
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US Patent 7526748 Design pattern data preparing method, mask pattern data preparing method, mask manufacturing method, semiconductor device manufacturing method, and program recording medium
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US Patent 7526749 Methods and apparatus for designing and using micro-targets in overlay metrology
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US Patent 7530035 Automatic power grid synthesis method and computer readable recording medium for storing program thereof
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US Patent 7530040 Automatically routing nets according to current density rules
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US Patent 7530043 Printed circuit board able to suppress simultaneous switching noise
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US Patent 7530048 Defect filtering optical lithography verification process
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US Patent 7530049 Mask manufacturing system, mask data creating method and manufacturing method of semiconductor device
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US Patent 7533362 Allocating hardware resources for high-level language code sequences
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US Patent 7536662 Method for recognizing and verifying FIFO structures in integrated circuit designs
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US Patent 7539960 Reducing a parasitic graph in moment computation algorithms in VLSI systems
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US Patent 7543252 Migration of integrated circuit layout for alternating phase shift masks
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US Patent 7543257 Apparatus for giving assistance in analyzing deficiency in RTL-input program and method of doing the same
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US Patent 7546569 Automatic trace determination method
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US Patent 7552407 Method and system for performing target enlargement in the presence of constraints
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US Patent 7552412 Integrated circuit (IC) chip design method, program product and system
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US Patent 7555737 Auxiliary method for circuit design
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US Patent 7562315 Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout
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US Patent 7562317 Multitasking circuit layout diagram silkscreen text handling method and system
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US Patent 7562322 Design verification for a switching network logic using formal techniques
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US Patent 7562329 Master-slice-type semiconductor integrated circuit having a bulk layer and a plurality of wiring layers and a design method therefor
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US Patent 7565639 Integrated assist features for epitaxial growth bulk tiles with compensation
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US Patent 7571399 Process for checking the quality of the metallization of a printed circuit
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US Patent 7581198 Method and system for the modular design and layout of integrated circuits
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US Patent 7584437 Assuring correct data entry to generate shells for a semiconductor platform
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US Patent 7584439 Cell modeling for integrated circuit design with characterization of upstream driver strength
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US Patent 7584446 Method and apparatus for extending processing time in one pipeline stage
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US Patent 7594197 Semiconductor device having predictable electrical properties
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US Patent 7594202 Optimization of circuit designs using a continuous spectrum of library cells
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US Patent 7594213 Method and apparatus for computing dummy feature density for chemical-mechanical polishing
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US Patent 7600203 Circuit design system and circuit design program
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US Patent 7600209 Generating constraint preserving testcases in the presence of dead-end constraints
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US Patent 7603636 Assertion generating system, program thereof, circuit verifying system, and assertion generating method
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US Patent 7603647 Recognition of a state machine in high-level integrated circuit description language code
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US Patent 7603648 Mask design using library of corrections
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US Patent 7607117 Representing device layout using tree structure
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US Patent 7614023 System for estimating a terminal capacitance and for characterizing a circuit
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US Patent 7617464 Verifying an IC layout in individual regions and combining results
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US Patent 7617466 Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device
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US Patent 7617470 Reconfigurable integrated circuit and method for increasing performance of a reconfigurable integrated circuit
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US Patent 7617474 System and method for providing defect printability analysis of photolithographic masks with job-based automation
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US Patent 7620924 Base platforms with combined ASIC and FPGA features and process of using the same
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US Patent 7627840 Method for soft error modeling with double current pulse
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US Patent 7627848 Bit stream compatible FPGA to MPGA conversions
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US Patent 7631287 Calculating method, verification method, verification program and verification system for edge deviation quantity, and semiconductor device manufacturing method
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US Patent 7634744 Semiconductor memory device and method for generating ROM data pattern
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US Patent 7634747 Trace delay error compensation
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US Patent 7636904 Locating critical dimension(s) of a layout feature in an IC design by modeling simulated intensities
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US Patent 7644383 Method and system for correcting signal integrity crosstalk violations
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US Patent 7647573 Method and device for testing delay paths of an integrated circuit
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US Patent 7647574 Basic cell design method for reducing the resistance of connection wiring between logic gates
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US Patent 7650584 Application specific semiconductor integrated circuit and its manufacturing method thereof
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US Patent 7650587 Local coloring for hierarchical OPC
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US Patent 7657852 System and technique of pattern matching and pattern replacement
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US Patent 7657859 Method for IC wiring yield optimization, including wire widening during and after routing
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US Patent 7661080 Method and apparatus for net-aware critical area extraction
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US Patent 7665044 Method and system for the condensed macro library creation
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US Patent 7665052 Method and mechanism for performing timing aware via insertion
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US Patent 7669155 Generic methodology to support chip level integration of IP core instance constraints in integrated circuits
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US Patent 7669165 Method and system for equivalence checking of a low power design
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US Patent 7673267 Method and apparatus for reducing jitter in an integrated circuit
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US Patent 7673273 MPGA products based on a prototype FPGA
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US Patent 7673276 Method and system for conducting a low-power design exploration
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US Patent 7676772 Layout description having enhanced fill annotation
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US Patent 7681164 Method and apparatus for placing an integrated circuit device within an integrated circuit layout
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US Patent 7685545 Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow
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US Patent 7685556 Mask data correction method, photomask manufacturing method, computer program, optical image prediction method, resist pattern shape prediction method, and semiconductor device manufacturing method
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US Patent 7689942 Simultaneous power and timing optimization in integrated circuits by performing discrete actions on circuit components
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US Patent 7689951 Design rule checking system and method, for checking compliance of an integrated circuit design with a plurality of design rules
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US Patent 7689958 Partitioning for a massively parallel simulation system
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US Patent 7689966 Methods, systems, and carrier media for evaluating reticle layout data
‌
US Patent 7689968 Proximity effect correction with regard to a semiconductor circuit design pattern
‌
US Patent 7694244 Modeling and cross correlation of design predicted criticalities for optimization of semiconductor manufacturing
‌
US Patent 7694247 Identification of ESD and latch-up weak points in an integrated circuit
‌
US Patent 7694251 Method and system for verifying power specifications of a low power design
‌
US Patent 7694255 Variable delay circuit, recording medium, logic verification method and electronic device
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US Patent 7694257 Method and apparatus for deep sub-micron design of integrated circuits
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US Patent 7694265 Operational cycle assignment in a configurable IC
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US Patent 7698675 Method and design system for semiconductor integrated circuit with a reduced placement area
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US Patent 7698676 Method and system for improving manufacturability of integrated devices
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US Patent 7703051 Trimming temperature coefficients of electronic components and circuits
‌
US Patent 7703053 Regional pattern density determination method and system
‌
US Patent 7703057 Systems and methods to determine ground capacitances of non-floating nets
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US Patent 7703059 Method and apparatus for automatic creation and placement of a floor-plan region
‌
US Patent 7703065 FPGA with hybrid interconnect
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US Patent 7703067 Range pattern definition of susceptibility of layout regions to fabrication issues
‌
US Patent 7707526 Predicting IC manufacturing yield based on hotspots
‌
US Patent 7707537 Method and apparatus for generating layout regions with local preferred directions
‌
US Patent 7712069 Method for interlayer and yield based optical proximity correction
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US Patent 7712071 Printing a mask with maximum possible process window through adjustment of the source distribution
‌
US Patent 7716608 Circuit synthesis with sequential rules
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US Patent 7716613 Method for classifying errors in the layout of a semiconductor circuit
‌
US Patent 7716621 Method and system for improving signal integrity in integrated circuit designs
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US Patent 7721238 Method and apparatus for configurable printed circuit board circuit layout pattern
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US Patent 7721239 Semiconductor integrated circuit with connecting lines for connecting conductive lines of a memory cell array to a driver
‌
US Patent 7721241 Automated method and tool for documenting a transformer design
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US Patent 7721246 Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout
‌
US Patent 7725852 Sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture
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US Patent 7735048 Achieving fast parasitic closure in a radio frequency integrated circuit synthesis flow
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US Patent 7739639 Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer
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US Patent 7743352 Computer implemented method of high-level synthesis for the efficient verification of computer software
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US Patent 7743359 Apparatus and method for photomask design
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US Patent 7747977 Method and system for stencil design for particle beam writing
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US Patent 7757190 Design rules checking augmented with pattern matching
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US Patent 7757196 Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards
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US Patent 7757199 Logic description library of differential input circuit
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US Patent 7761823 Method for adjusting a transistor model for increased circuit simulation accuracy
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US Patent 7765515 Pattern match based optical proximity correction and verification of integrated circuit layout
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US Patent 7770139 Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path
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US Patent RE41548 FPGA with hybrid interconnect
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US Patent 7779371 Methods, systems and user interface for evaluating product designs in light of promulgated standards
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US Patent 7779372 Clock gater with test features and low setup time
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US Patent 7779376 Operation analysis method of semiconductor integrated circuit
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US Patent 7779379 Template-based gateway model routing system
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US Patent 7784007 Method for automatically producing layout information
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US Patent 7784012 System and method for creating a standard cell library for use in circuit designs
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US Patent 7784013 Method for the definition of a library of application-domain-specific logic cells
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US Patent 7788608 Microbump function assignment in a buck converter
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US Patent 7788621 Method and apparatus for creating layout model, computer product, and method of manufacturing device
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US Patent 7788625 Method and apparatus for precharacterizing systems for use in system level design of integrated circuits
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US Patent 7793239 Method and system of modeling leakage
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US Patent 7793251 Method for increasing the manufacturing yield of programmable logic devices
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US Patent 7797653 Circuit verification apparatus, circuit verification method, and signal distribution method for the same
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US Patent 7797664 System for configuring an integrated circuit and method thereof
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US Patent 7802214 Methods and apparatuses for timing analysis of electronics circuits
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US Patent 7805688 Memory construction apparatus for forming logical memory space
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US Patent 7805691 Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program
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US Patent 7805697 Rotary clock synchronous fabric
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US Patent 7810053 Method and system of dynamic power cutoff for active leakage reduction in circuits
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US Patent 7810058 Early power estimator for integrated circuits
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US Patent 7810063 Graphical user interface for prototyping early instance density
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US Patent 7814452 Function symmetry-based optimization for physical synthesis of programmable integrated circuits
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US Patent 7814456 Method and system for topography-aware reticle enhancement
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US Patent 7818705 Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew
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US Patent 7823091 Compilable, reconfigurable network processor
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US Patent 7823096 Inductance analysis system and method and program therefor
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US Patent 7823097 Unrolling hardware design generate statements in a source window debugger
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US Patent 7823099 Lithography suspect spot location and scoring system
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US Patent 7823104 Determination of single-fix rectification function
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US Patent 7831950 Method and system for designing printed circuit board for electronic circuit
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US Patent 7836415 Circuit design method and circuit design system for calculating power consumption considering IR-drop
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US Patent 7836419 Method and system for partitioning integrated circuits
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US Patent 7840916 Structure for on-chip electromigration monitoring system
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US Patent 7840920 Method of generating test program for operating semiconductor testing apparatus
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US Patent 7840922 Semiconductor design support apparatus
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US Patent 7840927 Mutable cells for use in integrated circuits
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US Patent 7844926 Specification window violation identification with application in semiconductor device design
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US Patent 7849431 CMOS inverter layout for increasing effective channel length
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US Patent 7849436 Method of forming dummy pattern
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US Patent 7853920 Method for detecting, sampling, analyzing, and correcting marginal patterns in integrated circuit manufacturing
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US Patent 7856607 System and method for generating at-speed structural tests to improve process and environmental parameter space coverage
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US Patent 7856611 Reconfigurable interconnect for use in software-defined radio systems
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US Patent 7861192 Technique to implement clock-gating using a common enable for a plurality of storage cells
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US Patent 7861208 Structure for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks
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US Patent 7861209 Method for interlayer and yield based optical proximity correction
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US Patent 7865857 System and method for improved visualization and debugging of constraint circuit objects
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US Patent 7865860 Layout design device and layout method
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US Patent 7865862 Design structure for dynamically selecting compiled instructions
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US Patent 7870518 Predictive event scheduling in an iterative resolution network
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US Patent 7870534 Method and apparatus for creating wiring model, computer product, and method of manufacturing device
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US Patent 7873922 Structure for robust cable connectivity test receiver for high-speed data receiver
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US Patent 7873929 Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correction
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US Patent 7877720 Method and tool for designing electronic circuits on a printed circuit board
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US Patent 7882452 Modeling silicon-on-insulator stress effects
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US Patent 7882477 Method and apparatus for creating layout model, computer product, and method of manufacturing device
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US Patent 7890912 Treatment of trim photomask data for alternating phase shift lithography
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US Patent 7895549 Method and apparatus for implementing a processor interface block with an electronic design automation tool
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US Patent 7895562 Adaptive weighting method for layout optimization with multiple priorities
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US Patent 7900170 System and method correcting optical proximity effect using pattern configuration dependent OPC models
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US Patent 7900176 Transistor layout structures for controlling sizes of transistors without changing active regions, and methods of controlling the same
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US Patent 7900184 Decoder using a memory for storing state metrics implementing a decoder trellis
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US Patent 7904862 Method and mechanism for performing clearance-based zoning
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US Patent 7904864 Interconnect layer of a modularly designed analog integrated circuit
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US Patent 7904867 Integrating a boolean SAT solver into a router
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US Patent 7904874 Opposite-phase scheme for peak current reduction
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US Patent 7908576 Method of progressively prototyping and validating a customer's electronic system design
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US Patent 7908578 Methods for designing semiconductor device with dynamic array section
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US Patent 7908579 Method and mechanism for extraction and recognition of polygons in an IC design
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US Patent 7913205 Method and system for reversing the effects of sequential reparameterization on traces
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US Patent 7913206 Method and mechanism for performing partitioning of DRC operations
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US Patent 7917874 Reversing the effects of sequential reparameterization on traces
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US Patent 7917876 Method and apparatus for designing an embedded system for a programmable logic device
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US Patent 7917881 Timing of a circuit design
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US Patent 7921384 System, methods and apparatuses for integrated circuits for nanorobotics
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US Patent 7921388 Wordline booster design structure and method of operating a wordine booster circuit
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US Patent 7921390 Method and system for creating, viewing, editing, and sharing output from a design checking system
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US Patent 7921396 Data aligner in reconfigurable computing environment
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US Patent 7926014 Clock-gating circuit insertion method, clock-gating circuit insertion program and designing apparatus
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US Patent 7926020 Methods for automatically generating assertions
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US Patent 7926021 Insertion of error detection circuits based on error propagation within integrated circuits
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US Patent 7930660 Measurement structure in a standard cell for controlling process parameters during manufacturing of an integrated circuit
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US Patent 7930671 Test method for unit re-modification
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US Patent 7930672 Incremental design reduction via iterative overapproximation and re-encoding strategies
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US Patent 7930674 Modifying integrated circuit designs to achieve multiple operating frequency targets
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US Patent 7934176 Method and apparatus for determining a process model that models the impact of a CAR/PEB on the resist profile
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US Patent 7934177 Method and system for a pattern layout split
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US Patent 7934189 Method of making an integrated circuit including simplifying metal shapes
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US Patent 7937674 Method, system, and computer program product for predicting thin film integrity, manufacturability, reliability, and performance in electronic designs
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US Patent 7945870 Method and apparatus for detecting lithographic hotspots in a circuit layout
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US Patent 7945872 Verifying an IC layout in individual regions and combining results
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US Patent 7945882 Asynchronous circuit logical verification method, logical verification apparatus, and computer readable storage medium
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US Patent 7949973 Methods of implementing multi-cycle paths in electronic circuits
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US Patent 7949987 Method and system for implementing abstract layout structures with parameterized cells
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US Patent 7954080 Method and apparatus for de-embedding on-wafer devices
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US Patent 7958469 Design structure for a phase locked loop with stabilized dynamic response
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US Patent 7958483 Clock throttling based on activity-level signals
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US Patent 7962873 Fast evaluation of average critical area for ic layouts
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US Patent 7962878 Method of making an integrated circuit using pre-defined interconnect wiring
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US Patent 7962880 Wire structures minimizing coupling effects between wires in a bus
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US Patent 7962882 Fast evaluation of average critical area for IC layouts
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US Patent 7962884 Floorplanning apparatus and computer readable recording medium storing floorplanning program
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US Patent 7962886 Method and system for generating design constraints
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US Patent 7971159 Data generating method, data generating device, and program in an exposure system for irradiating multigradation-controllable spotlights
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US Patent 7975250 Allocation of combined or separate data and control planes
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US Patent 7975251 Method, recording medium, and design support system for designing an electronics device
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US Patent 7979833 Debugging simulation of a circuit core using pattern recorder, player and checker
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US Patent 7984393 System and method for making photomasks
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US Patent 7984398 Automated multiple voltage/power state design process and chip description system
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US Patent 7992113 Methods and apparatus for decision making in resolution based SAT-solvers
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US Patent 7992117 System and method for designing a common centroid layout for an integrated circuit
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US Patent 7992123 Method of engineering change to semiconductor circuit executable in computer system
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US Patent 7996795 Method and apparatus for performing stress modeling of integrated circuit material undergoing material conversion
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US Patent 7996800 Computer program product for design verification using sequential and combinational transformations
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US Patent 7996806 Methods and apparatus for layout of multi-layer circuit substrates
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US Patent 7996810 System and method for designing a low leakage monotonic CMOS logic circuit
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US Patent 8001503 Method and system for automatically accessing internal signals or ports in a design hierarchy
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US Patent 8001505 Method and apparatus for merging EDA coverage logs of coverage data
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US Patent 8010913 Model-based assist feature placement using inverse imaging approach
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US Patent 8010916 Test yield estimate for semiconductor products created from a library
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US Patent 8010926 Clock power minimization with regular physical placement of clock repeater components
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US Patent 8010929 Method and apparatus for generating layout regions with local preferred directions
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US Patent 7996810 System and method for designing a low leakage monotonic CMOS logic circuit
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US Patent 7992113 Methods and apparatus for decision making in resolution based SAT-solvers
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US Patent 7992117 System and method for designing a common centroid layout for an integrated circuit
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US Patent 7984398 Automated multiple voltage/power state design process and chip description system

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