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Hung Vu

based in Utah

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Edits on 20 Aug, 2022
"Infobox creation from: https://mobile.twitter.com/hunghvu_dev"
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Golden AI
edited on 20 Aug, 2022
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Location
Washington, Utah
Washington, Utah
"Edit from table cell"
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godwinno feliks
edited on 20 Aug, 2022
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Twitter URL
https://mobile.twitter.com/hunghvu_dev
Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
Edits made to:
Infobox (-134 properties)
Infobox
Patent primary examiner of
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US Patent 7087982 Nitrogen-containing polymers as porogens in the preparation of highly porous, low dielectric constant materials
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US Patent 7091555 Semiconductor device for switching
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US Patent 7091592 Stacked package for electronic elements and packaging method thereof
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US Patent 7098503 Circuitry and capacitors comprising roughened platinum layers
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US Patent 7102237 ASIC customization with predefined via mask
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US Patent 7109081 Capacitor for semiconductor device and method of forming the same
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US Patent 7109568 Semiconductor device including n-channel fets and p-channel fets with improved drain current characteristics
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US Patent 7109582 Semiconductor device for testing semiconductors
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US Patent 7109590 Semiconductor component comprising a surface metallization
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US Patent 7112495 Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
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US Patent 7112864 Module for optical device, and manufacturing method therefor
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US Patent 7115897 Semiconductor circuit configuration and semiconductor memory device
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US Patent 7115951 Low triggering voltage ESD protection structure and method for reducing the triggering voltage
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US Patent 7115966 Semiconductor device
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US Patent 7122827 Monolithic light emitting devices based on wide bandgap semiconductor nanostructures and methods for making same
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US Patent 7122836 Electro-optical device and electronic apparatus
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US Patent 7122910 Packaged semiconductor device
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US Patent 7129165 Method and structure to improve reliability of copper interconnects
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US Patent 7129591 Semiconductor device having align key and method of fabricating the same
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US Patent 7132685 Asymmetry thin-film transistor
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US Patent 7135753 Structure and method for III-nitride monolithic power IC
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US Patent 7135760 Moisture resistant integrated circuit leadframe package
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US Patent 7135775 Enhancement of an interconnect
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US Patent 7138683 Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processes
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US Patent 7141860 LDMOS transistor
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US Patent 7141883 Integrated circuit package configuration incorporating shielded circuit element structure
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US Patent 7144807 Low resistivity titanium silicide on heavily doped semiconductor
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US Patent 7145229 Silicone metalization
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US Patent 7145244 Hardening of copper to improve copper CMP performance
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US Patent 7145245 Low-k dielectric film with good mechanical strength that varies in local porosity depending on location on substrate—therein
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US Patent 7148538 Vertical NAND flash memory array
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US Patent 7148565 Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
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US Patent 7148569 Pad surface finish for high routing density substrate of BGA packages
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US Patent 7148574 Bonding pad structure and method of forming the same
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US Patent 7164166 Memory circuit with spacers between ferroelectric layer and electrodes
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US Patent 7172968 Ultra thin, single phase, diffusion barrier for metal conductors
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US Patent 7180089 Reconfigurable organic light-emitting device and display apparatus employing the same
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US Patent 7180153 Capture of residual refractory metal within semiconductor device
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US Patent 7180179 Thermal interposer for thermal management of semiconductor devices
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US Patent 7187044 Complementary metal gate electrode technology
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US Patent 7187069 Semiconductor device
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US Patent 7190043 Techniques to create low K ILD for beol
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US Patent 7193291 Organic Schottky diode
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US Patent 7193323 Electroplated CoWP composite structures as copper barrier layers
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US Patent 7193329 Semiconductor device
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US Patent 7196369 Plasma damage protection circuit for a semiconductor device
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US Patent 7196422 Low-dielectric constant structure with a multilayer stack of thin films with pores
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US Patent 7205617 Semiconductor device including active regions and gate electrodes for field effect transistors, with a trench formed between the active regions
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US Patent 7208377 Silicon oxidation method
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US Patent 7211872 Device having recessed spacers for improved salicide resistance on polysilicon gates
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US Patent 7214976 Solid-state imaging device with floating diffusion layer
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US Patent 7215008 In-line apparatus and method for manufacturing double-sided stacked multi-chip packages
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US Patent 7217979 Semiconductor apparatus including a radiator for diffusing the heat generated therein
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US Patent 7221015 Semiconductor device and method of manufacturing the same
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US Patent 7223615 High emissivity capacitor structure
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US Patent 7224004 Compound semiconductor device and method of fabricating the same
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US Patent 7226843 Indium-boron dual halo MOSFET
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US Patent 7229921 Semiconductor device and manufacturing method for the same
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US Patent 7230270 Self-aligned double gate device and method for forming same
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US Patent 7233052 Semiconductor device including fine dummy patterns
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US Patent 7235451 Drain extended MOS devices with self-aligned floating region and fabrication methods therefor
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US Patent 7235866 Low dielectric constant film material, film and semiconductor device using such material
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US Patent 7239012 Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers
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US Patent 7242068 Photosensitive semiconductor package, method for fabricating the same, and lead frame thereof
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US Patent 7242096 Semiconductor device and method for manufacturing the same
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US Patent 7245018 Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof
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US Patent 7250631 Semiconductor laser having protruding portion
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US Patent 7250657 Layout structure for memory arrays with SOI devices
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US Patent 7250661 Semiconductor memory device with plural source/drain regions
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US Patent 7256089 Top electrode barrier for on-chip die de-coupling capacitor and method of making same
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US Patent 7259401 Reflection-type optoelectronic semiconductor device
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US Patent 7262459 Semiconductor device and method of manufacturing the semiconductor device
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US Patent 7262494 Three-dimensional package
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US Patent 7268383 Capacitor and method of manufacturing a capacitor
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US Patent 7268419 Interposer containing bypass capacitors for reducing voltage noise in an IC device
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US Patent 7271452 Analog switch
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US Patent 7271476 Wiring substrate for mounting semiconductor components
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US Patent 7271490 Semiconductor device having dummy wiring layers and a method for manufacturing the same
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US Patent 7271492 Photo mask set for forming multi-layered interconnection lines and semiconductor device fabricated using the same
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US Patent 7279353 Passivation planarization
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US Patent 7279359 High performance amine based no-flow underfill materials for flip chip applications
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US Patent 7279735 Flash memory device
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US Patent 7282768 MOS field-effect transistor
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US Patent 7285816 Content addressable matrix memory cell
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US Patent 7288786 Integrated circuit configuration with analysis protection and method for producing the configuration
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US Patent 7291886 Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
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US Patent 7291920 Semiconductor structures
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US Patent 7294886 Power semiconductor device
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US Patent 7298017 Actuation using lithium/metal alloys and actuator device
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US Patent 7303969 Method of making interband tunneling diodes
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US Patent 7304386 Semiconductor device having a multilayer wiring structure
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US Patent 7309626 Quasi self-aligned source/drain FinFET process
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US Patent 7309923 Integrated circuit package having stacked integrated circuits and method therefor
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US Patent 7315087 Angled elongated features for improved alignment process integration
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US Patent 7316954 Methods of fabricating integrated circuit devices that utilize doped poly-Si
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US Patent 7319267 Semiconductor device
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US Patent 7326976 Corner dominated trigate field effect transistor
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US Patent 7329922 Dual-gate metal-oxide semiconductor device
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US Patent 7335608 Materials, structures and methods for microelectronic packaging
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US Patent 7339196 Packaging of SMD light emitting diodes
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US Patent 7342269 Photoelectric conversion device, and process for its fabrication
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US Patent 7342292 Capacitor assembly having a contact electrode encircling or enclosing in rectangular shape an effective capacitor area
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US Patent 7348633 Hybrid crystallographic surface orientation substrate having one or more SOI regions and/or bulk semiconductor regions
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US Patent 7352026 EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same
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US Patent 7354797 Method for producing a plurality of electronic devices
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US Patent 7358549 Multi-layered metal routing technique
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US Patent 7358557 Capacitor for semiconductor device and method of forming the same
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US Patent 7361955 High-voltage MOS device with dummy diffusion region
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US Patent 7361959 CMOS circuits including a passive element having a low end resistance
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US Patent 7365364 Sensor semiconductor device with sensor chip
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US Patent 7365404 Semiconductor device having silicide reaction blocking region
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US Patent 7378732 Semiconductor package
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US Patent 7381610 Semiconductor transistors with contact holes close to gates
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US Patent 7387935 Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method
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US Patent 7391066 Imager floating diffusion region and process for forming same
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US Patent 7391092 Integrated circuit including a temperature monitor element and thermal conducting layer
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US Patent 7391094 Semiconductor structure and method of making same
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US Patent 7393733 Methods of forming hybrid fin field-effect transistor structures
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US Patent 7400018 End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping
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US Patent 7400036 Semiconductor chip package with a package substrate and a lid cover
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US Patent 7405481 Glue layer for adhesion improvement between conductive line and etch stop layer in an integrated circuit chip
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US Patent 7407879 Chemical planarization performance for copper/low-k interconnect structures
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US Patent 7408239 Capture of residual refractory metal within semiconductor device
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US Patent 7410836 Method for fabricating a photosensitive semiconductor package
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US Patent 7411256 Semiconductor integrated circuit device capacitive node interconnect
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US Patent 7411258 Cobalt disilicide structure
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US Patent 7411261 MEMS device and fabrication method thereof
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US Patent 7414323 Tab tape and method of manufacturing the same
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US Patent 7417251 Active matrix organic EL display device and manufacturing method thereof
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US Patent 7417260 Multiple-chromatic light emitting device
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US Patent 7417301 Semiconductor component with coreless transformer
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US Patent 7417328 External power ring with multiple tapings to reduce IR drop in integrated circuit
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US Patent 7696052 Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions
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US Patent 7951701 Semiconductor device having elastic solder bump to prevent disconnection
Edits on 7 Dec, 2021
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7951701 Semiconductor device having elastic solder bump to prevent disconnection
Edits on 4 Dec, 2021
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Golden AI
edited on 4 Dec, 2021
Edits on 1 Dec, 2021
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7417328 External power ring with multiple tapings to reduce IR drop in integrated circuit
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7417301 Semiconductor component with coreless transformer
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7417260 Multiple-chromatic light emitting device
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7417251 Active matrix organic EL display device and manufacturing method thereof
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7414323 Tab tape and method of manufacturing the same
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7411256 Semiconductor integrated circuit device capacitive node interconnect
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7411261 MEMS device and fabrication method thereof
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7411258 Cobalt disilicide structure
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7410836 Method for fabricating a photosensitive semiconductor package
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7408239 Capture of residual refractory metal within semiconductor device
Golden AI profile picture
Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7407879 Chemical planarization performance for copper/low-k interconnect structures
Golden AI profile picture
Golden AI
edited on 30 Nov, 2021
Golden AI profile picture
Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7400036 Semiconductor chip package with a package substrate and a lid cover
Golden AI profile picture
Golden AI
edited on 30 Nov, 2021
Edits on 30 Nov, 2021
Golden AI profile picture
Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7393733 Methods of forming hybrid fin field-effect transistor structures

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