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Alexander Ghyka

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Edits on 14 Dec, 2021
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7087443 Optimized temperature controller for cold mass introduction
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US Patent 7087507 Implantation of deuterium in MOS and DRAM devices
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US Patent 7087512 Method for fabricating connection regions of an integrated circuit, and integrated circuit having connection regions
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US Patent 7091070 Semiconductor device and method of manufacturing the same
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US Patent 7091134 Deposition of integrated circuit fabrication materials using a print head
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US Patent 7094693 Method of manufacturing semiconductor device and semiconductor device
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US Patent 7098145 Fabrication of self-assembled monolayers
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US Patent 7098152 Adhesive support method for wafer coating, thinning and backside processing
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US Patent 7119034 Atomic layer deposition method of forming an oxide comprising layer on a substrate
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US Patent 7119391 System and method of manufacturing a substrate device
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US Patent 7122880 Compositions for preparing low dielectric materials
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US Patent 7125781 Methods of forming capacitor devices
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US Patent 7125809 Method and material for removing etch residue from high aspect ratio contact surfaces
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US Patent 7125813 Method of depositing low K barrier layers
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US Patent 7129155 Process for producing a plurality of gate stacks which are approximately the same height and equidistant on a semiconductor substrate
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US Patent 7135408 Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure
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US Patent 7135421 Atomic layer-deposited hafnium aluminum oxide
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US Patent 7138299 Method of electrically connecting a microelectronic component
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US Patent 7138336 Plasma enhanced atomic layer deposition (PEALD) equipment and method of forming a conducting thin film using the same thereof
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US Patent 7138340 Method for fabricating semiconductor device without damaging hard mask during contact formation process
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US Patent 7144432 Method of making capacitor element used for solid electrolytic capacitor
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US Patent 7144783 Reducing gate dielectric material to form a metal gate electrode extension
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US Patent 7145191 P-channel field-effect transistor with reduced junction capacitance
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US Patent 7148156 Removable amorphous carbon CMP stop
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US Patent 7148157 Use of phoslon (PNO) for borderless contact fabrication, etch stop/barrier layer for dual damascene fabrication and method of forming phoslon
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US Patent 7151007 Doped organic semiconductor materials and process for their preparation
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US Patent 7151015 Semiconductor device and manufacturing method thereof
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US Patent 7153718 Micromechanical component as well as a method for producing a micromechanical component
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US Patent 7153786 Method of fabricating lanthanum oxide layer and method of fabricating MOSFET and capacitor using the same
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US Patent 7157364 Method for forming metal contacts on a substrate
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US Patent 7160799 Define via in dual damascene process
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US Patent 7160818 Semiconductor device and method for fabricating same
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US Patent 7160821 Method of depositing low k films
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US Patent 7163901 Methods for forming thin film layers by simultaneous doping and sintering
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US Patent 7172964 Method of preventing photoresist poisoning of a low-dielectric-constant insulator
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US Patent 7176092 Gate electrode for a semiconductor fin device
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US Patent 7176123 Method for manufacturing metal line of semiconductor device
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US Patent 7179743 Titanium underlayer for lines in semiconductor devices
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US Patent 7179751 Hydrogen plasma photoresist strip and polymeric residue cleanup process for low dielectric constant materials
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US Patent 7183192 Composition for removing photoresist and method of forming a bump electrode in a semiconductor device using the composition
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US Patent 7186629 Protecting thin semiconductor wafers during back-grinding in high-volume production
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US Patent 7189630 Layer sequence for producing a composite material for electromechanical components
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US Patent 7189638 Method for manufacturing metal structure using trench
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US Patent 7189647 Sequential station tool for wet processing of semiconductor wafers
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US Patent 7192846 Methods and systems for processing a device, methods and systems for modeling same and the device
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US Patent 7192893 Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off
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US Patent 7198966 Electron-emitting device, electron source, image-forming apparatus, and method for producing electron-emitting device and electron-emitting apparatus
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US Patent 7199030 Method of manufacturing semiconductor device
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US Patent 7199040 Barrier layer structure
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US Patent 7199061 Pecvd silicon oxide thin film deposition
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US Patent 7199064 Plasma processing method and apparatus
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US Patent 7202162 Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materials
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US Patent 7202166 Surface preparation prior to deposition on germanium
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US Patent 7205167 Method to detect photoresist residue on a semiconductor device
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US Patent 7205248 Method of eliminating residual carbon from flowable oxide fill
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US Patent 7205249 CVD plasma assisted low dielectric constant films
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US Patent 7205250 Plasma processing method and apparatus
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US Patent 7208383 Method of manufacturing a semiconductor component
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US Patent 7208411 Method of depositing metal film and metal deposition cluster tool including supercritical drying/cleaning module
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US Patent 7208412 Method of forming metal oxide and semimetal oxide
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US Patent 7211463 Process to improve carrier mobility of organic semiconductor
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US Patent 7211493 Variable capacitor structure and method of manufacture
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US Patent 7214597 Electronic components and method of fabricating the same
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US Patent 7214609 Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
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US Patent 7220684 Semiconductor device and method of manufacturing the same
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US Patent 7223676 Very low temperature CVD process with independently variable conformality, stress and composition of the CVD layer
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US Patent 7223705 Ambient gas treatment of porous dielectric
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US Patent 7229907 Method of forming a damascene structure with integrated planar dielectric layers
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US Patent 7229916 Method of manufacturing a semiconductor device
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US Patent 7232767 Slotted electrostatic shield modification for improved etch and CVD process uniformity
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US Patent 7232768 Hydrogen plasma photoresist strip and polymeric residue cleanup process for low dielectric constant materials
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US Patent 7238627 Organosilicate polymer and insulating film therefrom
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US Patent 7241688 Aperture masks for circuit fabrication
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US Patent 7250331 Mask for crystallizing and method of crystallizing amorphous silicon using the same
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US Patent 7253102 Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers
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US Patent 7253107 Pressure control system
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US Patent 7259067 Method for manufacturing flash memory device
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US Patent 7259112 Method for minimizing corner effect by densifying the insulating layer
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US Patent 7262129 Minimizing resist poisoning in the manufacture of semiconductor devices
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US Patent 7265013 Sidewall image transfer (SIT) technologies
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US Patent 7265062 Ionic additives for extreme low dielectric constant chemical formulations
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US Patent 7271022 Process for forming microstructures
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US Patent 7271094 Multiple shadow mask structure for deposition shadow mask protection and method of making and using same
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US Patent 7271096 Method for improved deposition of dielectric material
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US Patent 7271100 Slurry composition, polishing method using the slurry composition and method of forming a gate pattern using the slurry composition
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US Patent 7273821 Method for producing a porous coating
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US Patent 7273823 Situ oxide cap layer development
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US Patent 7276402 Semiconductor device and manufacturing method thereof
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US Patent 7276426 Methods of forming semiconductor constructions
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US Patent 7279432 System and method for forming an integrated barrier layer
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US Patent 7279435 Apparatus for stabilizing high pressure oxidation of a semiconductor device
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US Patent 7282441 De-fluorination after via etch to preserve passivation
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US Patent 7282457 Apparatus for stabilizing high pressure oxidation of a semiconductor device
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US Patent 7285440 Organic underlayers that improve the performance of organic semiconductors
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US Patent 7285503 Hermetic cap layers formed on low-k films by plasma enhanced chemical vapor deposition
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US Patent 7288435 Method for producing a cover, method for producing a packaged device
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US Patent 7291545 Plasma immersion ion implantation process using a capacitively couple plasma source having low dissociation and low minimum plasma voltage
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US Patent 7291547 Filter device and method for fabricating filter devices
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US Patent 7294209 Apparatus and method for depositing material onto a substrate using a roll-to-roll mask
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US Patent 7294563 Semiconductor on insulator vertical transistor fabrication and doping process
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US Patent 7294585 Compositions for preparing low dielectric materials
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US Patent 7300856 Process for detaching layers of material
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US Patent 7300890 Method and apparatus for forming conformal SiN
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US Patent 7303952 Method for fabricating doped polysilicon lines
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US Patent 7303982 Plasma immersion ion implantation process using an inductively coupled plasma source having low dissociation and low minimum plasma voltage
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US Patent 7303991 Atomic layer deposition methods
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US Patent 7303992 Copper electrodeposition in microelectronics
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US Patent 7304004 System and method for forming a gate dielectric
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US Patent 7306956 Variable temperature and dose atomic layer deposition
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US Patent 7309658 Molecular self-assembly in substrate processing
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US Patent 7309662 Method and apparatus for forming a film on a substrate
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US Patent 7314768 Formation method of electroconductive pattern, and production method of electron-emitting device, electron source, and image display apparatus using this
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US Patent 7316983 Film formation apparatus and film formation method and cleaning method
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US Patent 7319068 Method of depositing low k barrier layers
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US Patent 7319070 Semiconductor device fabrication method
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US Patent 7320944 Deposition of phosphosilicate glass film
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US Patent 7320946 Method for generating dynamic mask pattern
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US Patent 7323390 Semiconductor device and method for production thereof
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US Patent 7326581 System, method and apparatus for automatic control of an RF generator for maximum efficiency
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US Patent 7326610 Process options of forming silicided metal gates for advanced CMOS devices
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US Patent 7326619 Method of manufacturing integrated circuit device including recessed channel transistor
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US Patent 7329615 Atomic layer deposition method of forming an oxide comprising layer on a substrate
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US Patent 7335540 Low temperature polysilicon thin film transistor and method of manufacturing the same
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US Patent 7335595 Silicide formation using a low temperature anneal process
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US Patent 7338896 Formation of deep via airgaps for three dimensional wafer to wafer interconnect
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US Patent 7338900 Method for forming tungsten nitride film
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US Patent 7338905 Semiconductor device manufacture method
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US Patent 7338910 Method of fabricating semiconductor devices and method of removing a spacer
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US Patent 7341909 Methods of forming semiconductor constructions
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US Patent 7341947 Methods of forming metal-containing films over surfaces of semiconductor substrates
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US Patent 7344982 System and method of selectively depositing Ruthenium films by digital chemical vapor deposition
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US Patent 7348674 Low capacitance wiring layout
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US Patent 7351596 Method and system for operating a physical vapor deposition process
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US Patent 7351659 Methods of forming a transistor with an integrated metal silicide gate electrode
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US Patent 7358109 Surface emitting laser package having integrated optical element and alignment post
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US Patent 7358142 Method for forming a FinFET by a damascene process
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US Patent 7358169 Laser-assisted deposition
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US Patent 7358187 Coating process for patterned substrate surfaces
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US Patent 7358188 Method of forming conductive metal silicides by reaction of metal with silicon
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US Patent 7358195 Method for fabricating liquid crystal display device
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US Patent 7361610 Method of etching a glass substrate
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US Patent 7365029 Method for silicon nitride chemical vapor deposition
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US Patent 7368297 Method for forming catalytic sites at the surface of a support
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US Patent 7368375 Electronic component with compliant elevations having electrical contact areas and method for producing it
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US Patent 7368382 Atomic layer deposition methods
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US Patent 7368824 Diffusion solder position, and process for producing it
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US Patent 7371677 Laterally grown nanotubes and method of formation
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US Patent 7381645 Method for the production of an integrated circuit bar arrangement comprising a metal nitride layer and integrated circuit arrangement
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US Patent 7384860 Method of manufacturing a semiconductor device
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US Patent 7393720 Method for fabricating electrical interconnect structure
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US Patent RE40507 Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG
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US Patent 7988743 Method for manufacturing solid electrolytic capacitor
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US Patent 7989346 Surface treatment of silicon
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7989346 Surface treatment of silicon
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7988743 Method for manufacturing solid electrolytic capacitor
Edits on 1 Dec, 2021
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Golden AI
edited on 1 Dec, 2021
Edits on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7393720 Method for fabricating electrical interconnect structure
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7384860 Method of manufacturing a semiconductor device
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Golden AI
edited on 30 Nov, 2021
Edits on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7371677 Laterally grown nanotubes and method of formation
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368824 Diffusion solder position, and process for producing it
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368382 Atomic layer deposition methods
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Golden AI
edited on 26 Nov, 2021
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368297 Method for forming catalytic sites at the surface of a support
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7365029 Method for silicon nitride chemical vapor deposition
Edits on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7361610 Method of etching a glass substrate
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7358195 Method for fabricating liquid crystal display device
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7358188 Method of forming conductive metal silicides by reaction of metal with silicon
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7358187 Coating process for patterned substrate surfaces
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7358169 Laser-assisted deposition
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7358142 Method for forming a FinFET by a damascene process
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7358109 Surface emitting laser package having integrated optical element and alignment post

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