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John P Trimmings

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Edits on 14 Dec, 2021
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7310758 Circuit for and method of implementing programmable logic devices
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US Patent 7315973 Method and apparatus for choosing tests for simulation and associated algorithms and hierarchical bipartite graph data structure
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US Patent 7325176 System and method for accelerated information handling system memory testing
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US Patent 7328385 Method and apparatus for measuring digital timing paths by setting a scan mode of sequential storage elements
‌
US Patent 7346829 Semiconductor device and testing method for same
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US Patent 7350124 Method and apparatus for accelerating through-the pins LBIST simulation
‌
US Patent 7353442 On-chip and at-speed tester for testing and characterization of different types of memories
‌
US Patent 7356743 RRAM controller built in self test memory
‌
US Patent 7360127 Method and apparatus for evaluating and optimizing a signaling system
‌
US Patent 7363556 Testing apparatus and testing method
‌
US Patent 7363564 Method and apparatus for securing communications ports in an electronic device
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US Patent 7370247 Dynamic offset compensation based on false transitions
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US Patent 7370249 Method and apparatus for testing a memory array
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US Patent 7373564 Semiconductor memory
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US Patent 7373567 System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA
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US Patent 7373569 Pulsed flop with scan circuitry
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US Patent 7373570 LSI device having scan separators provided in number reduced from signal lines of combinatorial circuits
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US Patent 7373571 Achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques
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US Patent 7373572 System pulse latch and shadow pulse latch coupled to output joining circuit
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US Patent 7373577 CAN system
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US Patent 7376875 Method of improving logical built-in self test (LBIST) AC fault isolations
‌
US Patent 7376889 Memory device capable of detecting its failure
‌
US Patent 7380184 Sequential scan technique providing enhanced fault coverage in an integrated circuit
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US Patent 7383477 Interface circuit for using a low voltage logic tester to test a high voltage IC
‌
US Patent 7383478 Wireless dynamic boundary-scan topologies for field
‌
US Patent 7383481 Method and apparatus for testing a functional circuit at speed
‌
US Patent 7386767 Programmable bit error rate monitor for serial interface
‌
US Patent 7386768 Memory channel with bit lane fail-over
‌
US Patent 7389455 Register file initialization to prevent unknown outputs during test
‌
US Patent 7395462 Defect estimation apparatus and related method
‌
US Patent 7395466 Method and apparatus to adjust voltage for storage location reliability
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US Patent 7395475 Circuit and method for fuse disposing in a semiconductor memory device
‌
US Patent 7398445 Method and system for debug and test using replicated logic
‌
US Patent 7404115 Self-synchronising bit error analyser and circuit
‌
US Patent 7404124 On-chip sampling circuit and method
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US Patent 7415646 Page
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US Patent 7421629 Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure
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US Patent 7424656 Clocking methodology for at-speed testing of scan circuits with synchronous clocks
‌
US Patent 7426668 Performing memory built-in-self-test (MBIST)
‌
US Patent 7428674 Monitoring the state vector of a test access port
‌
US Patent 7434114 Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same
‌
US Patent 7434120 Test mode control circuit
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US Patent 7437629 Method for checking the refresh function of an information memory
‌
US Patent 7437635 Testing hard-wired IP interface signals using a soft scan chain
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US Patent 7437638 Boundary-Scan methods and apparatus
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US Patent 7437644 Automatic self-testing of an internal device in a closed system
‌
US Patent 7441165 Read-only memory and operational control method thereof
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US Patent 7441169 Semiconductor integrated circuit with test circuit
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US Patent 7444558 Programmable measurement mode for a serial point to point link
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US Patent 7444570 Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test
‌
US Patent 7444571 Apparatus and method for testing and debugging an integrated circuit
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US Patent 7444572 Built-in self test for a thermal processing system
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US Patent 7444573 VLCT programmation/read protocol
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US Patent 7444574 Stimulus extraction and sequence generation for an electric device under test
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US Patent 7444577 Memory device testing to support address-differentiated refresh rates
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US Patent 7447948 ECC coding for high speed implementation
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US Patent 7447954 Method of testing a memory module and hub of the memory module
‌
US Patent 7447955 Test apparatus and test method
‌
US Patent 7447956 Method and apparatus for testing data steering logic for data storage having independently addressable subunits
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US Patent 7447966 Hardware verification scripting
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US Patent 7454674 Digital jitter detector
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US Patent 7454676 Method for testing semiconductor chips using register sets
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US Patent 7461308 Method for testing semiconductor chips by means of bit masks
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US Patent 7461311 Device and method for creating a signature
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US Patent 7461312 Digital signature generation for hardware functional test
‌
US Patent 7461317 System and method for aligning a quadrature encoder and establishing a decoder processing speed
‌
US Patent 7467342 Method and apparatus for embedded built-in self-test (BIST) of electronic circuits and systems
‌
US Patent 7472318 System and method for determining on-chip bit error rate (BER) in a communication system
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US Patent 7472322 On-chip interface trap characterization and monitoring
‌
US Patent 7475297 Efficient method for computing clock skew without pessimism
‌
US Patent 7475307 Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain
‌
US Patent 7475311 Systems and methods for diagnosing rate dependent errors using LBIST
‌
US Patent 7475313 Unique pBIST features for advanced memory testing
‌
US Patent 7475315 Configurable built in self test circuitry for testing memory arrays
‌
US Patent 7478289 System and method for improving the yield of integrated circuits containing memory
‌
US Patent 7478294 Time controllable sensing scheme for sense amplifier in memory IC test
‌
US Patent 7478298 Method and system for backplane testing using generic boundary-scan units
‌
US Patent 7478300 Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device
‌
US Patent 7478301 Partial good integrated circuit and method of testing same
‌
US Patent 7478302 Signal integrity self-test architecture
‌
US Patent 7478304 Apparatus for accelerating through-the-pins LBIST simulation
‌
US Patent 7480839 Qualified anomaly detection
‌
US Patent 7480840 Apparatus, system, and method for facilitating port testing of a multi-port host adapter
‌
US Patent 7484135 Semiconductor device having a mode of functional test
‌
US Patent 7484140 Memory having variable refresh control and method therefor
‌
US Patent 7484143 System and method for providing testing and failure analysis of integrated circuit memory devices
‌
US Patent 7484146 Method for capturing multiple data packets in a data signal for analysis
‌
US Patent 7484147 Semiconductor integrated circuit
‌
US Patent 7484153 Systems and methods for LBIST testing using isolatable scan chains
‌
US Patent 7484156 Apparatus and method for testing PS/2 interface
‌
US Patent 7487419 Reduced-pin-count-testing architectures for applying test patterns
‌
US Patent 7487421 Emulation cache access for tag view reads
‌
US Patent 7493544 Extending test sequences to accepting states
‌
US Patent 7496809 Integrated scannable interface for testing memory
‌
US Patent 7496810 Semiconductor memory device and its data writing method
‌
US Patent 7496812 Apparatus and method for testing and debugging an integrated circuit
‌
US Patent 7496813 Communicating simultaneously a functional signal and a diagnostic signal for an integrated circuit using a shared pin
‌
US Patent 7496815 Method and apparatus for automatic generation of system test libraries
‌
US Patent 7496818 Apparatus and method for testing and debugging an integrated circuit
‌
US Patent 7496820 Method and apparatus for generating test vectors for an integrated circuit under test
‌
US Patent 7500161 Correcting test system calibration and transforming device measurements when using multiple test fixtures
‌
US Patent 7500162 Sourcing internal signals to output pins of an integrated circuit through sequential multiplexing
‌
US Patent 7500164 Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies
‌
US Patent 7502974 Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets
‌
US Patent 7502989 Even-load software Reed-Solomon decoder
‌
US Patent 7506222 System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling
‌
US Patent 7506226 System and method for more efficiently using error correction codes to facilitate memory device testing
‌
US Patent 7506234 Signature circuit, semiconductor device having the same and method of reading signature information
‌
US Patent RE40684 Fast cyclic redundancy check (CRC) generation
‌
US Patent 7509545 Method and system for testing memory modules
‌
US Patent 7512846 Method and apparatus of defect areas management
‌
US Patent 7512847 Method for estimating and reporting the life expectancy of flash-disk memory
‌
US Patent 7512850 Checkpointing user design states in a configurable IC
‌
US Patent 7516374 Testing circuit and related method of injecting a time jitter
‌
US Patent 7516376 Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product
‌
US Patent 7516383 Method and apparatus for analyzing delay in circuit, and computer product
‌
US Patent 7519878 Obtaining test data for a device
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US Patent 7519883 Method of configuring a system and system therefor
‌
US Patent 7519886 Apparatus and method for integrated functional built-in self test for an ASIC
‌
US Patent 7519889 System and method to reduce LBIST manufacturing test time of integrated circuits
‌
US Patent 7519890 Input/output circuit for handling unconnected I/O pads
‌
US Patent 7526693 Initial decision-point circuit operation mode
‌
US Patent 7533310 Semiconductor memory test device and method thereof
‌
US Patent 7533311 Programmable management IO pads for an integrated circuit
‌
US Patent 7533313 Method and apparatus for identifying outlier data
‌
US Patent 7533315 Integrated circuit with scan-based debugging and debugging method thereof
‌
US Patent 7536614 Built-in-redundancy analysis using RAM
‌
US Patent 7536615 Logic analyzer systems and methods for programmable logic devices
‌
US Patent 7539913 Systems and methods for chip testing
‌
US Patent 7543196 Apparatus for testing integrated circuit
‌
US Patent 7543199 Test device
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US Patent 7549092 Output controller with test unit
‌
US Patent 7549101 Clock transferring apparatus, and testing apparatus
‌
US Patent 7555689 Generating responses to patterns stimulating an electronic circuit with timing exception paths
‌
US Patent 7555690 Device for and method of coupling test signals to a device under test
‌
US Patent 7558992 Reducing the soft error vulnerability of stored data
‌
US Patent 7558994 Methods and apparatus for data compression
‌
US Patent 7559001 Method and apparatus for executing commands and generation of automation scripts and test cases
‌
US Patent 7562276 Apparatus and method for testing and debugging an integrated circuit
‌
US Patent 7565586 Method and apparatus for latent fault memory scrub in memory intensive computer hardware
‌
US Patent 7568135 Use of alternative value in cell detection
‌
US Patent 7568141 Method and apparatus for testing embedded cores
‌
US Patent 7571363 Parametric measurement of high-speed I/O systems
‌
US Patent 7574633 Test apparatus, adjustment method and recording medium
‌
US Patent 7574634 Real time testing using on die termination (ODT) circuit
‌
US Patent 7574644 Functional pattern logic diagnostic method
‌
US Patent 7577885 Semiconductor integrated circuit, design support software system and automatic test pattern generation system
‌
US Patent 7577887 JTAG interface device of mobile terminal and method thereof
‌
US Patent 7587645 Input circuit of semiconductor memory device and test system having the same
‌
US Patent 7590903 Re-configurable architecture for automated test equipment
‌
US Patent 7590911 Apparatus and method for testing and debugging an integrated circuit
‌
US Patent 7590912 Using a chip as a simulation engine
‌
US Patent 7594150 Fault-tolerant architecture of flip-flops for transient pulses and signal delays
‌
US Patent 7596729 Memory device testing system and method using compressed fail data
‌
US Patent 7596737 System and method for testing state retention circuits
‌
US Patent 7603595 Memory test circuit and method
‌
US Patent 7603596 Memory device capable of detecting its failure
‌
US Patent 7603598 Semiconductor device for testing semiconductor process and method thereof
‌
US Patent 7607056 Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices
‌
US Patent 7607057 Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip
‌
US Patent 7613971 Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit
‌
US Patent 7613974 Fault detection method and apparatus
‌
US Patent 7617425 Method for at-speed testing of memory interface using scan
‌
US Patent 7617426 Verification method and apparatus
‌
US Patent 7617431 Method and apparatus for analyzing delay defect
‌
US Patent 7620861 Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels
‌
US Patent 7624310 System and method for initializing a memory system, and memory device and processor-based system using same
‌
US Patent 7624317 Parallel bit test circuit and method for semiconductor memory device
‌
US Patent 7627791 Method and apparatus for recording a data stream on a storage medium
‌
US Patent 7627798 Systems and methods for circuit testing using LBIST
‌
US Patent 7627799 Panel driving circuit that generates panel test pattern and panel test method thereof
‌
US Patent 7640463 On-chip receiver eye finder circuit for high-speed serial link
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US Patent 7644323 Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identification
‌
US Patent 7644324 Semiconductor memory tester
‌
US Patent 7644327 System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA
‌
US Patent 7650540 Detecting and differentiating SATA loopback modes
‌
US Patent 7650544 Test mode control circuit
‌
US Patent 7650548 Power saving flip-flop
‌
US Patent 7650553 Semiconductor integrated circuit apparatus and interface test method
‌
US Patent 7653844 Communication apparatus and communication system
‌
US Patent 7653847 Methods and structure for field flawscan in a dynamically mapped mass storage device
‌
US Patent 7653852 Semiconductor device and method of adding tester circuit for the same
‌
US Patent 7657798 Semiconductor integrated circuit and the same checking method
‌
US Patent 7657799 Method and apparatus for testing a dual mode interface
‌
US Patent 7661039 Self-synchronizing bit error analyzer and circuit
‌
US Patent 7661051 System to reduce programmable range specifications for a given target accuracy in calibrated electronic circuits
‌
US Patent 7665004 Timing generator and semiconductor testing apparatus
‌
US Patent 7673193 Processor-memory unit for use in system-in-package and system-in-module devices
‌
US Patent 7673205 Semiconductor IC and testing method thereof
‌
US Patent 7673206 Method and system for routing scan chains in an array of processor resources
‌
US Patent 7673207 Method for at speed testing of devices
‌
US Patent 7676711 Test circuit for testing command signal at package level in semiconductor device
‌
US Patent 7681096 Semiconductor integrated circuit, BIST circuit, design program of BIST circuit, design device of BIST circuit and test method of memory
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US Patent 7685489 Semiconductor integrated circuit and testing method
‌
US Patent 7702972 Method and apparatus for SRAM macro sparing in computer chips
‌
US Patent 7702981 Structural testing using boundary scan techniques
‌
US Patent 7707467 Input/output compression and pin reduction in an integrated circuit
‌
US Patent 7711998 Test circuit arrangement
‌
US Patent 7721167 Apparatus and method for testing and debugging an integrated circuit
‌
US Patent 7721170 Apparatus and method for selectively implementing launch off scan capability in at speed testing
‌
US Patent 7721171 Scheme to optimize scan chain ordering in designs
‌
US Patent 7725780 Enabling memory redundancy during testing
‌
US Patent 7725782 Linked random access memory (RAM) interleaved pattern persistence strategy
‌
US Patent 7725783 Method and apparatus for repeatable drive strength assessments of high speed memory DIMMs
‌
US Patent 7730373 Test data compression method for system-on-chip using linear-feedback shift register reseeding
‌
US Patent 7734966 Method and system for memory testing and test data reporting during memory testing
‌
US Patent 7734967 Semiconductor memory device and testing method of the same
‌
US Patent 7734973 Testing apparatus and testing method for an integrated circuit, and integrated circuit
‌
US Patent 7739563 Semiconductor integrated circuit and memory test method
‌
US Patent 7739572 Tester for testing semiconductor device
‌
US Patent 7739573 Voltage identifier sorting
‌
US Patent 7743291 Semiconductor memory device
‌
US Patent 7743294 Diagnostic mode switching
‌
US Patent 7743301 Semiconductor integrated circuit and method of testing same
‌
US Patent 7752513 Method and circuit for LSSD testing
‌
US Patent 7757137 Method and apparatus for on-the-fly minimum power state transition
‌
US Patent 7761753 Memory channel with bit lane fail-over
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US Patent 7761757 Apparatus and method of setting test mode in semiconductor integrated circuit
‌
US Patent 7761764 System and method for self-test of integrated circuits
‌
US Patent 7770080 Using neighborhood functions to extract logical models of physical failures using layout based diagnosis
‌
US Patent 7770081 Interface circuit for a single logic input pin of an electronic system
‌
US Patent 7774671 Method and apparatus to adjust voltage for storage location reliability
‌
US Patent 7779316 Method of testing memory array at operational speed using scan
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US Patent 7783938 Result directed diagnostic method and system
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US Patent 7783940 Apparatus for redundancy reconfiguration of faculty memories
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US Patent 7788561 Diagnosing mixed scan chain and system logic defects
‌
US Patent 7793171 Protocol tester and method for performing a protocol test
‌
US Patent 7793177 Chip testing device and system
‌
US Patent 7793184 Lowering power consumption during logic built-in self-testing (LBIST) via channel suppression
‌
US Patent 7797591 Semiconductor integrated circuit, design support software system, and automatic test pattern generation system
‌
US Patent 7797596 Method for monitoring and adjusting circuit performance
‌
US Patent 7802152 Method and apparatus for recording high-speed input data into a matrix of memory devices
‌
US Patent 7802154 Method and apparatus for generating high-frequency command and address signals for high-speed semiconductor memory device testing
‌
US Patent 7802160 Test apparatus and calibration method
‌
US Patent RE41787 Method and circuit for generating a tracking error signal using differential phase detection
‌
US Patent 7810005 Method and system for correcting timing errors in high data rate automated test equipment
‌
US Patent 7810006 Testing system for a device under test
‌
US Patent 7818635 Digital broadcast receiver
‌
US Patent 7818638 Systems and devices including memory with built-in self test and methods of making and using the same
‌
US Patent 7823031 Method and system for testing semiconductor memory device using internal clock signal of semiconductor memory device as data strobe signal
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US Patent 7831874 Local defect memories on semiconductor substrates in a stack computer
‌
US Patent 7831876 Testing a circuit with compressed scan chain subsets
‌
US Patent 7831879 Generating test coverage bin based on simulation result
‌
US Patent 7831881 Apparatus and method for hybrid detection of memory data
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US Patent 7840859 Block interleaving with memory table of reduced size
‌
US Patent 7844869 Implementing enhanced LBIST testing of paths including arrays
‌
US Patent 7844876 Temperature sampling in electronic devices
‌
US Patent 7849373 Method of testing a memory module and hub of the memory module
‌
US Patent 7849387 Detecting architectural vulnerability of processor resources
‌
US Patent 7853840 Semiconductor memory device and methods thereof
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US Patent 7853842 Semiconductor memory device with ZQ calibration
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US Patent 7853846 Locating hold time violations in scan chains by generating patterns on ATE
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US Patent 7861128 Scan element with self scan-mode toggle
‌
US Patent 7865789 System and method for system-on-chip interconnect verification
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US Patent 7865795 Methods and apparatuses for generating a random sequence of commands for a semiconductor device
‌
US Patent 7877659 Memory model for functional verification of multi-processor systems
‌
US Patent 7877668 Memory access system
‌
US Patent 7882406 Built in test controller with a downloadable testing program
‌
US Patent 7882409 Method and apparatus for synthesis of augmented multimode compactors
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US Patent 7886206 Semiconductor memory test device and method thereof
‌
US Patent 7890830 Test signal generating apparatus
‌
US Patent 7895479 System and method for initializing a memory system, and memory device and processor-based system using same
‌
US Patent 7895484 Semiconductor device, memory system and control method of the semiconductor device
‌
US Patent 7900099 Enabling test modes of individual integrated circuit devices out of a plurality of integrated circuit devices
‌
US Patent 7900112 System and method for digital logic testing
‌
US Patent 7904763 Reception device, reception method, information processing device, information processing method, and program
‌
US Patent 7904768 Probing system for integrated circuit devices
‌
US Patent 7913142 Method for testing at least one arithmetic unit installed in a control unit
‌
US Patent 7917821 System-on-chip performing multi-phase scan chain and method thereof
‌
US Patent 7917823 Decoupled clocking in testing architecture and method of testing
‌
US Patent 7917825 Method and apparatus for selectively utilizing information within a semiconductor device
‌
US Patent 7921346 Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD)
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US Patent 7925949 Embedded processor
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US Patent 7930601 AC ABIST diagnostic method, apparatus and program product
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US Patent 7930604 Apparatus and method for testing and debugging an integrated circuit
‌
US Patent 7930609 Apparatus and method for verifying target circuit
‌
US Patent 7945822 Storing data to multi-chip low-latency random read memory device using non-aligned striping
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US Patent 7945824 Processor-memory unit for use in system-in-package and system-in-module devices
‌
US Patent 7945831 Gating TDO from plural JTAG circuits
‌
US Patent 7949913 Method for creating a memory defect map and optimizing performance using the memory defect map
‌
US Patent 7949914 Diagnostic mode switching
‌
US Patent 7949915 Method and apparatus for describing parallel access to a system-on-chip
‌
US Patent 7949919 Microelectronic device and pin arrangement method thereof
‌
US Patent 7949920 DFT techniques to reduce test time and power for SoCs
‌
US Patent 7954015 Data interleaving and deinterleaving involving concatenation of words read from storage
‌
US Patent 7958413 Method and system for memory testing and test data reporting during memory testing
‌
US Patent 7958438 CAN system
‌
US Patent 7962807 Semiconductor storage apparatus managing system, semiconductor storage apparatus, host apparatus, program and method of managing semiconductor storage apparatus
‌
US Patent 7971113 Method for detecting disturb phenomena between neighboring blocks in non-volatile memory
‌
US Patent 7975193 Solid state storage end of life prediction with correction history
‌
US Patent 7975198 Test system and back annotation method
‌
US Patent 7979754 Voltage margin testing for proximity communication
‌
US Patent 7979759 Test and bring-up of an enhanced cascade interconnect memory system
‌
US Patent 7984341 Method, system and computer program product involving error thresholds
‌
US Patent 7984343 Inter-device connection test circuit generating method, generation apparatus, and its storage medium
‌
US Patent 7984345 Test apparatus and test method
‌
US Patent 7984346 Integrated apparatus for testing image devices
‌
US Patent 7984350 Logic circuitry and recording medium
‌
US Patent 7984354 Generating responses to patterns stimulating an electronic circuit with timing exception paths
‌
US Patent 8001453 CAN system
‌
US Patent 8006148 Test mode control circuit and method for using the same in semiconductor memory device
‌
US Patent 8006154 Semiconductor integrated circuit and method for testing semiconductor integrated circuit
‌
US Patent 8010854 Method and circuit for brownout detection in a memory system
Edits on 8 Dec, 2021
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US Patent 8010854 Method and circuit for brownout detection in a memory system
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US Patent 8006154 Semiconductor integrated circuit and method for testing semiconductor integrated circuit
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Patent primary examiner of
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US Patent 8006148 Test mode control circuit and method for using the same in semiconductor memory device
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US Patent 8001453 CAN system
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US Patent 7984350 Logic circuitry and recording medium
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US Patent 7984346 Integrated apparatus for testing image devices
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US Patent 7984345 Test apparatus and test method
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Patent primary examiner of
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US Patent 7984341 Method, system and computer program product involving error thresholds
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edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7979754 Voltage margin testing for proximity communication
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edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7979759 Test and bring-up of an enhanced cascade interconnect memory system
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Patent primary examiner of
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US Patent 7975198 Test system and back annotation method
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Patent primary examiner of
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US Patent 7975193 Solid state storage end of life prediction with correction history
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edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7971113 Method for detecting disturb phenomena between neighboring blocks in non-volatile memory
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US Patent 7958438 CAN system
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US Patent 7958413 Method and system for memory testing and test data reporting during memory testing
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US Patent 7954015 Data interleaving and deinterleaving involving concatenation of words read from storage

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