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Roy K Potter
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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
US Patent 7378298 Method of making stacked die package
US Patent 7387936 Semiconductor device and method of fabricating the same
US Patent 7397112 Semiconductor package and lead frame therefor
US Patent 7399658 Pre-molded leadframe and method therefor
US Patent 7402896 Integrated circuit (IC) carrier assembly incorporating serpentine suspension
US Patent 7402899 Hermetically sealable silicon system and method of making same
US Patent 7405102 Methods and apparatus for thermal management in a multi-layer embedded chip structure
US Patent 7405105 Stack package using anisotropic conductive film (ACF) and method of making same
US Patent 7405135 Substrate for stressed systems and method of making same
US Patent 7405145 Ball grid array package substrates with a modified central opening and method for making the same
US Patent 7405456 Optical sensor chip package
US Patent 7407835 Localized slots for stress relieve in copper
US Patent 7413991 Damascene process at semiconductor substrate level
US Patent 7414324 Wafer structure with mirror shot
US Patent 7416918 Direct build-up layer on an encapsulated die package having a moisture barrier structure
US Patent 7419856 Methods of fabricating integrated circuit devices having fuse structures including buffer layers
US Patent 7425463 Stacked die package for peripheral and center device pad layout device
US Patent 7429783 Image sensor package
US Patent 7429795 Bond pad structure
US Patent 7429796 Semiconductor device and fabrication process thereof
US Patent 7432128 Method of making semiconductor device
US Patent 7432583 Leadless leadframe package substitute and stack package
US Patent 7432595 System and method to reduce metal series resistance of bumped chip
US Patent 7436059 Thermoelectric cooling device arrays
US Patent 7439585 Silicon-on-insulator device
US Patent 7439610 High power shunt switch with high isolation and ease of assembly
US Patent 7439620 Integrated circuit package-in-package system
US Patent 7442630 Method for fabricating forward and reverse blocking devices
US Patent 7443011 System and method for routing supply voltages or other signals between side-by-side die and a lead frame for system in a package (SIP) devices
US Patent 7443035 Method of forming a penetration electrode and substrate having a penetration electrode
US Patent 7445961 Semiconductor chip package and method for fabricating the same
US Patent 7446011 Array of cells including a selection bipolar transistor and fabrication method thereof
US Patent 7446029 Semiconductor element and manufacturing method thereof
US Patent 7446413 Circuit apparatus and method for operating the same
US Patent 7446420 Through silicon via chip stack package capable of facilitating chip selection during device operation
US Patent 7449750 Semiconductor protection device
US Patent 7449777 Circuit arrangement comprising a power component and a drive circuit integrated in two semiconductor bodies
US Patent 7449779 Wire bonded wafer level cavity package
US Patent 7449784 Device package and methods for the fabrication and testing thereof
US Patent 7453111 Phase-change memory device
US Patent 7453147 Semiconductor device, its manufacturing method, and radio communication device
US Patent 7453148 Structure of dielectric layers in built-up layers of wafer level package
US Patent 7456088 Integrated circuit package system including stacked die
US Patent 7459393 Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts
US Patent 7462508 Stack type semiconductor package module utilizing solder coated stacking protrusions and method for manufacturing the same
US Patent 7466020 Power module
US Patent 7468526 Semiconductor device, method of fabricating same, and electrooptical device
US Patent 7468556 Packaging of hybrid integrated circuits
US Patent 7470995 Integrated circuit (IC) carrier assembly with suspension means
US Patent 7473990 Semiconductor device featuring electrode terminals forming superior heat-radiation system
US Patent 7476567 Midair semiconductor device and manufacturing method of the same
US Patent 7476569 Leadframe enhancement and method of producing a multi-row semiconductor package
US Patent 7476979 Chip scale surface mounted device and process of manufacture
US Patent 7479698 Bonding pad structure disposed in semiconductor device and related method
US Patent 7479703 Integrated circuit package with sputtered heat sink for improved thermal performance
US Patent 7479706 Chip package structure
US Patent 7482681 Semiconductor device package utilizing proud interconnect material
US Patent 7482689 Microcomputer
US Patent 7485962 Semiconductor device, wiring substrate forming method, and substrate processing apparatus
US Patent 7485965 Through via in ultra high resistivity wafer and related methods
US Patent 7489026 Methods and apparatus for a Quad Flat No-Lead (QFN) package
US Patent 7491620 Method and structures for indexing dice
US Patent 7491994 Ferromagnetic memory cell and methods of making and using the same
US Patent 7492037 Package structure and lead frame using the same
US Patent 7492048 CMOS sensors having charge pushing regions
US Patent 7494838 Manufacturing method for magnetic sensor and lead frame therefor
US Patent 7494920 Method of fabricating a vertically mountable IC package
US Patent 7495255 Test pads on flash memory cards
US Patent 7495271 Image-sensing apparatus
US Patent 7495321 Leaded stacked packages having elevated die paddle
US Patent 7495324 Power semiconductor module
US Patent 7495338 Metal capped copper interconnect
US Patent 7498185 Light emitting diode and method making the same
US Patent 7498644 Prevention of tampering in electronic devices
US Patent 7498675 Semiconductor component having plate, stacked dice and conductive vias
US Patent 7501648 Phase change materials and associated memory devices
US Patent 7501658 Electro-luminescence device including a thin film transistor and method of fabricating an electro-luminescence device
US Patent 7501704 Integrated circuit chip with external pads and process for fabricating such a chip
US Patent 7501711 Epoxy resin composition for semiconductor encapsulation and semiconductor device using the same
US Patent 7504334 Semiconductor device and method for manufacturing same
US Patent 7504679 Enhancement mode GaN FET with piezoelectric gate
US Patent 7504720 Semiconductor unit, and power conversion system and on-vehicle electrical system using the same
US Patent 7508056 Surface mount hermetic package for power semiconductor die
US Patent 7508065 Device package and methods for the fabrication and testing thereof
US Patent 7511380 Semiconductor chip and method manufacturing the same
US Patent 7514718 LED package, manufacturing method thereof, and LED array module using the same
US Patent 7514797 Multi-die wafer level packaging
US Patent 7518220 Substrate for an FBGA semiconductor component
US Patent 7518225 Chip system architecture for performance enhancement, power reduction and cost reduction
US Patent 7521793 Integrated circuit mounting for thermal stress relief useable in a multi-chip module
US Patent 7521798 Stacked imager package
US Patent 7525124 Submount for light emitting diode and its manufacturing method
US Patent 7525185 Semiconductor device package having multi-chips with side-by-side configuration and method of the same
US Patent 7528010 Semiconductor component and method for producing the same
US Patent 7528470 Conductor board and method for producing a conductor board
US Patent 7528471 Integrated circuit incorporating wire bond inductance
US Patent 7528492 Test patterns for detecting misalignment of through-wafer vias
US Patent 7531451 SIP semiconductor device and method for manufacturing the same
US Patent 7531900 Package structure for electronic device
US Patent 7534658 Process for manufacturing microelectronic, microoptoelectronic or micromechanical devices
US Patent 7534664 Semiconductor device and method of manufacturing same
US Patent 7535101 Electrode pad on conductive semiconductor substrate
US Patent 7535110 Stack die packages
US Patent 7535114 Integrated circuit devices including compliant material under bond pads and methods of fabrication
US Patent 7537993 Methods of forming semiconductor devices having tunnel and gate insulating layers
US Patent 7538424 System and method for dissipating heat from a semiconductor module
US Patent 7538433 Semiconductor device
US Patent 7541612 Multi-chip package semiconductor device and method of detecting a failure thereof
US Patent 7541683 Semiconductor integrated circuit device
US Patent 7544577 Mobility enhancement in SiGe heterojunction bipolar transistors
US Patent 7550322 Manufacturing method for resin sealed semiconductor device
US Patent 7550840 Apparatus for effecting reliable heat transfer of bare die microelectronic device and method thereof
US Patent 7554126 Semiconductor light-emitting element, manufacturing method and mounting method of the same and light-emitting device
US Patent 7554203 Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture
US Patent RE40819 Semiconductor device with improved bond pads
US Patent 7557417 Module comprising a semiconductor chip comprising a movable element
US Patent 7557423 Semiconductor structure with a discontinuous material density for reducing eddy currents
US Patent 7557433 Microelectronic device with integrated energy source
US Patent 7557441 Package of MEMS device and method for fabricating the same
US Patent 7557443 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US Patent 7560762 Asymmetric floating gate NAND flash memory
US Patent 7560805 Semiconductor package and method of manufacturing the same
US Patent 7566956 Semiconductor composite device and method of manufacturing the same
US Patent 7566966 Integrated circuit package-on-package system with anti-mold flash feature
US Patent 7569421 Through-hole via on saw streets
US Patent 7569914 Semiconductor devices and method of manufacturing them
US Patent 7569935 Pillar-to-pillar flip-chip assembly
US Patent 7573071 Light emitting diode package
US Patent 7576405 Semiconductor integrated circuit for reducing leak current through MOS transistors
US Patent 7576434 Wafer-level solder bumps
US Patent 7576435 Low-cost and ultra-fine integrated circuit packaging technique
US Patent 7579267 Methods and systems for fabricating semiconductor components with through wire interconnects (TWI)
US Patent 7579678 Semiconductor microphone unit
US Patent 7579690 Semiconductor package structure
US Patent 7582952 Method for providing and removing discharging interconnect for chip-on-glass output leads and structures thereof
US Patent 7582955 Semiconductor device manufacturing method and manufacturing apparatus
US Patent 7582966 Semiconductor chip and method for fabricating the same
US Patent 7588993 Alignment for backside illumination sensor
US Patent 7589421 Heat-radiating semiconductor chip, tape wiring substrate and tape package using the same
US Patent 7592694 Chip package and method of manufacturing the same
US Patent 7598517 Superjunction trench device and method
US Patent 7602050 Integrated circuit packaging
US Patent 7605449 Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material
US Patent 7605472 Interconnections having double capping layer and method for forming the same
US Patent 7608890 Semiconductor device and method of manufacturing semiconductor device
US Patent 7611923 Method and apparatus for forming stacked die and substrate structures for increased packing density
US Patent 7615807 Field-effect transistor structures with gate electrodes with a metal layer
US Patent 7618900 Semiconductor device and method of fabricating semiconductor device
US Patent 7619273 Varactor
US Patent 7619315 Stack type semiconductor chip package having different type of chips and fabrication method thereof
US Patent 7622354 Integrated circuit and method of manufacturing an integrated circuit
US Patent 7622800 Stacked semiconductor packages and method therefor
US Patent 7626265 Semiconductor package having flexible lead connection plate for electrically connecting base and chip
US Patent 7633082 Light emitting device
US Patent 7635914 Multi layer low cost cavity substrate fabrication for pop packages
US Patent 7638869 Semiconductor device
US Patent 7642662 Semiconductor device and method of manufacturing the same
US Patent 7646094 Semiconductor device
US Patent 7648907 Semiconductor device, wiring substrate forming method, and substrate processing apparatus
US Patent 7649227 Semiconductor device and method of forming the same
US Patent 7651875 Catalysts
US Patent 7652340 Fin field effect transistor and method of manufacturing the same
US Patent 7652357 Quad flat no-lead (QFN) packages
US Patent 7652376 Integrated circuit package system including stacked die
US Patent 7656013 Multilayer wiring substrate, method of manufacturing the same, and semiconductor device
US Patent 7656034 Semiconductor device and method for manufacturing the same
US Patent 7659145 Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device
US Patent 7659609 Integrated circuit package-in-package system with carrier interposer
US Patent 7663213 Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same
US Patent 7663251 Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
US Patent 7667310 Paper including semiconductor device and manufacturing method thereof
US Patent 7667311 LSI package provided with interface module, and transmission line header employed in the package
US Patent 7667321 Wire bonding method and related device for high-frequency applications
US Patent 7675119 Semiconductor device and manufacturing method thereof
US Patent 7679109 Semiconductor device, layout design method thereof, and layout design device using the same
US Patent 7679199 Semiconductor apparatus
US Patent 7683464 Semiconductor package having dimpled plate interconnections
US Patent 7683465 Integrated circuit including clip
US Patent 7687893 Semiconductor package having leadframe with exposed anchor pads
US Patent 7687903 Power module and method of fabricating the same
US Patent 7687915 Semiconductor device having crack stop structure
US Patent 7692302 SIP semiconductor device and method for manufacturing the same
US Patent 7700404 Large die package structures and fabrication method therefor
US Patent 7705376 Sensor and method of manufacturing the same
US Patent 7705456 Semiconductor package substrate
US Patent 7709376 Method for fabricating semiconductor device and semiconductor device
US Patent 7709936 Module with carrier element
US Patent 7709966 Large substrate structural vias
US Patent 7713753 Dual-level self-assembled patterning method and apparatus fabricated using the method
US Patent 7713781 Methods for forming quad flat no-lead (QFN) packages
US Patent 7714337 Light emitting device and method of manufacturing the same
US Patent 7714416 Electronic circuit in a package-in-package configuration and production method
US Patent 7714436 Electronic device and electronic apparatus
US Patent 7714437 Semiconductor device and method for mounting semiconductor chip
US Patent 7718467 Memory device
US Patent 7718471 Method and apparatus for stacked die package with insulated wire bonds
US Patent 7723223 Method of doping transistor comprising carbon nanotube, method of controlling position of doping ion, and transistors using the same
US Patent 7732842 Structure and method for forming a planar schottky contact
US Patent 7732846 Semiconductor device including solid state image pickup device, and portable electronic apparatus
US Patent 7732880 Semiconductor device and method of manufacturing the same
US Patent 7732917 Power module
US Patent 7737540 Stacked semiconductor devices and signal distribution methods thereof
US Patent 7741711 Power semiconductor module with a connected substrate carrier and production method therefor
US Patent 7745901 Highly-depleted laser doped semiconductor volume
US Patent 7745916 Module comprising polymer-containing electrical connecting element
US Patent 7749791 Sensor and method of manufacturing the same
US Patent 7749900 Method and core materials for semiconductor packaging
US Patent 7750463 Bidirectional switch module
US Patent 7750474 Metal programmable logic and multiple function pin interface
US Patent 7750480 Semiconductor device
US Patent 7754536 Semiconductor device and fabrication process thereof
US Patent 7754562 Semiconductor device comprising capacitor and method of fabricating the same
US Patent 7755155 Packaging structure and method for fabricating the same
US Patent 7759780 Microelectronic package with wear resistant coating
US Patent 7759785 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
US Patent 7763980 Semiconductor die having a distribution layer
US Patent 7767540 Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility
US Patent 7768011 Electro-luminescence device including a thin film transistor and method of fabricating an electro-luminescence device
US Patent 7772618 Semiconductor storage device comprising MIS transistor including charge storage layer
US Patent 7781883 Electronic package with a thermal interposer and method of manufacturing the same
US Patent 7785927 Multi-die wafer level packaging
US Patent 7786481 Organic light emitting diode display and fabricating method thereof
US Patent 7786493 Light emitting diode, method for manufacturing light emitting diode, integrated light emitting diode, method for manufacturing integrated light emitting diode, light emitting diode backlight, light emitting diode illumination device, light emitting diode display, electronic apparatus, electronic device, and method for manufacturing electronic device
US Patent 7786556 Semiconductor device and lead frame used to manufacture semiconductor device
US Patent 7786559 Bezel packaging of frit-sealed OLED devices
US Patent 7790594 Electronic part and method of producing the same
US Patent 7790609 Method of forming metal line in semiconductor device
US Patent 7791145 Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures
US Patent 7791164 Electrical fuse, semiconductor device having the same, and method of programming and reading the electrical fuse
US Patent 7791191 Semiconductor device having multiple die redistribution layer
US Patent 7800103 Organic thin film transistor material, organic thin film transistor, field-effect transistor, switching element, organic semiconductor material and organic semiconductor film
US Patent 7804164 Subminiature electronic device having hermetic cavity and method of manufacturing the same
US Patent 7804172 Electrical connections made with dissimilar metals
US Patent 7807523 Sequential selective epitaxial growth
US Patent 7812363 Light emitting device module
US Patent 7812435 Integrated circuit package-in-package system with side-by-side and offset stacking
US Patent 7812465 Semiconductor chip having alignment mark and method of manufacturing the same
US Patent 7816765 Silicon epitaxial wafer and the production method thereof
US Patent 7816786 Semiconductor unit, and power conversion system and on-vehicle electrical system using the same
US Patent 7820548 Semiconductor device and manufacturing method thereof
US Patent 7821029 Electrostatic protection element
US Patent 7824961 Stacked imager package
US Patent 7825521 Stack die packages
US Patent 7829919 Semiconductor device
US Patent 7829981 Semiconductor device packages with electromagnetic interference shielding
US Patent 7829988 Stacking quad pre-molded component packages, systems using the same, and methods of making the same
US Patent 7830002 Device with chiplets and adaptable interconnections
US Patent 7833858 Superjunction trench device formation methods
US Patent 7834446 Electronic device and method for coping with electrostatic discharge
US Patent 7838863 Semiconductor devices having resistive memory elements
US Patent 7838975 Flip-chip package with fan-out WLCSP
US Patent 7838997 Remote chip attachment
US Patent RE41975 Interconnector line of thin film, sputter target for forming the wiring film and electronic component using the same
US Patent 7843023 Electromechanical switch
US Patent 7843032 Radio frequency identification device electrostatic discharge management
US Patent 7843040 Gallium nitride baseplate and epitaxial substrate
US Patent 7843046 Flat leadless packages and stacked leadless package assemblies
US Patent 7847365 MOSFET with isolation structure for monolithic integration and fabrication method thereof
US Patent 7847396 Semiconductor chip stack-type package and method of fabricating the same
US Patent 7851784 Nanotube array electronic devices
US Patent 7851848 Cylindrical channel charge trapping devices with effectively high coupling ratios
US Patent 7851921 Device mounting board having multiple circuit substrates, and semiconductor module with the device mounting board
US Patent 7858442 Leaded stacked packages having elevated die paddle
US Patent 7858445 Wire bonded wafer level cavity package
US Patent 7859056 Apparatus and methods for integrated circuit with devices with body contact and devices with electrostatic discharge protection
US Patent 7863606 Semiconductor-on-diamond devices and methods of forming
US Patent 7863717 Package structure of integrated circuit device and manufacturing method thereof
US Patent 7863735 Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof
US Patent 7868474 Method and structures for indexing dice
US Patent 7875873 Phase change materials and associated memory devices
US Patent 7875972 Semiconductor device assembly having a stress-relieving buffer layer
US Patent 7875973 Package substrate including surface mount component mounted on a peripheral surface thereof and microelectronic package including same
US Patent 7879654 Paper including semiconductor device and manufacturing method thereof
US Patent 7880274 Method of enabling alignment of wafer in exposure step of IC process after UV-blocking metal layer is formed over the whole wafer
US Patent 7880287 Stud bumps for die alignment
US Patent 7880292 Semiconductor device and fabricating method thereof
US Patent 7883936 Multi layer low cost cavity substrate fabrication for PoP packages
US Patent 7884463 Wiring board, semiconductor device and semiconductor element
US Patent 7884476 Semiconductor device
US Patent 7888731 Memory devices and methods of forming and operating the same
US Patent 7888758 Method of forming a permanent carrier and spacer wafer for wafer level optics and associated structure
US Patent 7888793 Device package and methods for the fabrication and testing thereof
US Patent 7888801 Semiconductor device
US Patent 7888802 Bonding pad structure and manufacturing method thereof
US Patent 7893482 Semiconductor devices having tunnel and gate insulating layers
US Patent 7898078 Power connector/decoupler integrated in a heat sink
US Patent 7901995 Interconnections resistant to wicking
US Patent 7902627 Capacitive isolation circuitry with improved common mode detector
US Patent 7902666 Flip chip device having soldered metal posts by surface mounting
US Patent 7915727 Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and electronic apparatus including the same
US Patent 7915730 Packaging conductive structure and method for manufacturing the same
US Patent 7919839 Support structures for on-wafer testing of wafer-level packages and multiple wafer stacked structures
US Patent 7919842 Structure and method for sealing cavity of micro-electro-mechanical device
US Patent 7919872 Integrated circuit (IC) carrier assembly with first and second suspension means
US Patent 7923739 Solid state lighting device
US Patent 7923839 Semiconductor device and method for fabricating semiconductor device
US Patent 7927924 Semi-finished package and method for making a package
US Patent 7928556 Semiconductor device and manufacturing method thereof
US Patent 7928567 Power supply network
US Patent 7932566 Structure and system of mixing poly pitch cell design under default poly pitch design rules
US Patent 7932567 Semiconductor device
US Patent 7936050 Semiconductor device and method of fabricating semiconductor device
US Patent 7936060 Reworkable electronic device assembly and method
US Patent 7939925 Semiconductor device and manufacturing method thereof
US Patent 7939927 Semiconductor memory apparatus
US Patent 7939928 Method and apparatus for stacked die package with insulated wire bonds
US Patent 7939944 Semiconductor die having a redistribution layer
US Patent 7943930 Semiconductor device forming method
US Patent 7944028 TFCC (TM) and SWCC (TM) thermal flex contact carriers
US Patent 7944029 Non-volatile memory with reduced mobile ion diffusion
US Patent 7951712 Interconnections having double capping layer and method for forming the same
US Patent 7952208 Substrate, manufacturing method thereof, method for manufacturing semiconductor device
US Patent 7955899 Method for providing and removing discharging interconnect for chip-on-glass output leads and structures thereof
US Patent 7956463 Large grain size conductive structure for narrow interconnect openings
US Patent 7956464 Sputtering target and semiconductor device manufactured using the same
US Patent 7960827 Thermal via heat spreader package and method
US Patent 7960839 Semiconductor interconnection line and method of forming the same
US Patent 7960841 Through-hole via on saw streets
US Patent 7964921 MOSFET and production method of semiconductor device
US Patent 7973394 Enhanced integrated circuit package
US Patent 7985984 III-nitride semiconductor field effect transistor
US Patent 7986027 Encapsulated metal resistor
US Patent 7986035 Multilayer wiring substrate, semiconductor package, and method of manufacturing semiconductor package
US Patent 7986040 Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices
US Patent 7989356 Semiconductor device and method of forming enhanced UBM structure for improving solder joint reliability
US Patent 7989936 Microelectronic device with integrated energy source
US Patent 7989948 Chip package structure and method of fabricating the same
US Patent 7994507 Electro-luminescence device including a thin film transistor and method of fabricating an electro-luminescence device
US Patent 7999373 Arrangement having at least one electronic component
US Patent 8008134 Large substrate structural vias
US Patent 8008782 Semiconductor device
US Patent 8009847 Hat with music player
Edits on 8 Dec, 2021
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 8009847 Hat with music player
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 8008782 Semiconductor device
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 8008134 Large substrate structural vias
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7999373 Arrangement having at least one electronic component
Golden AI
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Patent primary examiner of
US Patent 7994507 Electro-luminescence device including a thin film transistor and method of fabricating an electro-luminescence device
Golden AI
edited on 8 Dec, 2021
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US Patent 7989948 Chip package structure and method of fabricating the same
Golden AI
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US Patent 7989936 Microelectronic device with integrated energy source
Golden AI
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US Patent 7989356 Semiconductor device and method of forming enhanced UBM structure for improving solder joint reliability
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7986040 Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7986027 Encapsulated metal resistor
Golden AI
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Patent primary examiner of
US Patent 7986035 Multilayer wiring substrate, semiconductor package, and method of manufacturing semiconductor package
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7985984 III-nitride semiconductor field effect transistor
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7973394 Enhanced integrated circuit package
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7964921 MOSFET and production method of semiconductor device
Golden AI
edited on 7 Dec, 2021
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US Patent 7960841 Through-hole via on saw streets
Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
US Patent 7960839 Semiconductor interconnection line and method of forming the same
Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
US Patent 7960827 Thermal via heat spreader package and method
Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
US Patent 7956464 Sputtering target and semiconductor device manufactured using the same
Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
US Patent 7956463 Large grain size conductive structure for narrow interconnect openings
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