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Zandra V. Smith

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Megan Gustafson
edited on 23 Aug, 2022
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7087960 Semiconductor device including impurities in substrate via MOS transistor gate electrode and gate insulation film
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US Patent 7091084 Ultra-high capacitance device based on nanostructures
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US Patent 7091099 Bipolar transistor and method for fabricating the same
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US Patent 7091102 Methods of forming integrated circuit devices having a capacitor with a hydrogen barrier spacer on a sidewall thereof and integrated circuit devices formed thereby
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US Patent 7091121 Bumping process
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US Patent 7091513 Cathode assemblies
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US Patent 7094632 Low profile chip scale stacking system and method
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US Patent 7094662 Overlay mark and method of fabricating the same
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US Patent 7094674 Method for production of contacts on a wafer
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US Patent 7095046 Semiconductor device
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US Patent 7098147 Semiconductor memory device and method for manufacturing semiconductor device
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US Patent 7098501 Thin capacitive structure
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US Patent 7098502 Transistor having three electrically isolated electrodes and method of formation
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US Patent 7098537 Interconnect structure diffusion barrier with high nitrogen content
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US Patent 7098542 Multi-chip configuration to connect flip-chips to flip-chips
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US Patent 7099005 System for scatterometric measurements and applications
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US Patent 7099008 Alignment adjuster of probe, measuring instrument and alignment adjusting method of probe
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US Patent 7102169 Semiconductor device
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US Patent 7102185 Lightshield architecture for interline transfer image sensors
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US Patent 7102763 Methods and apparatus for processing microelectronic workpieces using metrology
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US Patent 7105363 Cladded conductor for use in a magnetoelectronics device and method for fabricating the same
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US Patent 7105426 Method of forming a semi-insulating region
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US Patent 7105427 Method for shallow dopant distribution
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US Patent 7105451 Method for manufacturing semiconductor device
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US Patent 7109086 Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique
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US Patent 7109105 Methods of making semiconductor fuses
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US Patent 7109121 Stress control of semiconductor microstructures for thin film growth
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US Patent 7110116 Alignment apparatus, exposure apparatus using same, and method of manufacturing devices
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US Patent 7112454 System and method for reducing shorting in memory cells
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US Patent 7112459 Thin film transistor liquid crystal display and fabrication method thereof
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US Patent 7112506 Method for forming capacitor of semiconductor device
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US Patent 7112508 Method for forming conductive material in opening and structure regarding same
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US Patent 7112513 Sub-micron space liner and densification process
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US Patent 7112531 Silicon oxide co-deposition/etching process
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US Patent 7112545 Passivation of material using ultra-fast pulsed laser
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US Patent 7112834 Gate etch process
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US Patent 7112871 Flipchip QFN package
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US Patent 7115442 Ball grid array package with stacked center pad chips and method for manufacturing the same
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US Patent 7115532 Methods of forming patterned photoresist layers over semiconductor substrates
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US Patent 7118987 Method of achieving improved STI gap fill with reduced stress
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US Patent 7119007 Production method of semiconductor device
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US Patent 7119012 Stabilization of Ni monosilicide thin films in CMOS devices using implantation of ions before silicidation
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US Patent 7119014 Method for fabricating a semiconductor device having a tapered-mesa side-wall film
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US Patent 7119431 Apparatus and method for forming heat sinks on silicon on insulator wafers
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US Patent 7122397 Method for manufacturing CMOS image sensor
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US Patent 7122414 Method to fabricate dual metal CMOS devices
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US Patent 7122463 Manufacturing method of semiconductor device
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US Patent 7122487 Method for forming an oxide with improved oxygen bonding
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US Patent 7122909 Wiring board, stacked wiring board and method of manufacturing the same, semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
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US Patent 7125736 Method of crystallizing a nitride III-V compound semiconductor layer on a sapphire substrate
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US Patent 7126166 High voltage lateral FET structure with improved on resistance performance
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US Patent 7129542 High voltage semiconductor device having high breakdown voltage and method of fabricating the same
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US Patent 7132339 Transistor structure with thick recessed source/drain structures and fabrication process of same
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US Patent 7132350 Method for manufacturing a programmable eraseless memory
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US Patent 7132677 Super bright light emitting diode of nanorod array structure having InGaN quantum well and method for manufacturing the same
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US Patent 11174153 Package level thermal gradient sensing
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US Patent 11177138 Double patterning method
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US Patent 11177145 Apparatus and method for manufacturing plurality of electronic circuits
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US Patent 11177170 Removal of barrier and liner layers from a bottom of a via
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US Patent 11177179 Method of manufacturing a semiconductor device and a semiconductor device
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US Patent 11177215 Integrated circuit device
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US Patent 11177336 Display substrate, repairing method thereof and display panel
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US Patent 7135416 Method of manufacturing semiconductor device
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US Patent 7135711 Electroluminescent body
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US Patent 7135712 Electroluminescent device
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US Patent 7135724 Structure and method for making strained channel field effect transistor using sacrificial spacer
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US Patent 7135736 Semiconductor device
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US Patent 7138318 Method of fabricating body-tied SOI transistor having halo implant region underlying hammerhead portion of gate
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US Patent 7138650 Semiconductor substrate, field-effect transistor, and their manufacturing method of the same
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US Patent 7138665 Light emitting element, method of manufacturing the same, and semiconductor device having light emitting element
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US Patent 7139073 Imaging apparatus
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US Patent 7141445 Semiconductor light emitting device and method for manufacturing same
‌
US Patent 7141461 Method for manufacturing a semiconductor device
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US Patent 7141819 Semiconductor package
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US Patent 7141837 High-density MOS transistor
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US Patent 7141852 Semiconductor device and fabricating method thereof
‌
US Patent 7144799 Method for pre-retaining CB opening
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US Patent 7145233 Decoupling capacitor closely coupled with integrated circuit
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US Patent 7148534 Angled implant in a fabrication technique to improve conductivity of a base material
‌
US Patent 7148540 Graded conductive structure for use in a metal-oxide-semiconductor device
‌
US Patent 7151041 Methods of forming semiconductor circuitry
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US Patent 7151049 Electroplating compositions and methods
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US Patent 7153714 Method of manufacturing flat panel displays
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US Patent 7154161 Composite ground shield for passive components in a semiconductor die
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US Patent 7154176 Conductive bumps with non-conductive juxtaposed sidewalls
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US Patent 7154189 Semiconductor device and method for fabricating the same
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US Patent 7157350 Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration
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US Patent 7157377 Method of making a semiconductor device using treated photoresist
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US Patent 7157733 Floating-gate field-effect transistors having doped aluminum oxide dielectrics
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US Patent 7157756 Field effect transistor
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US Patent 7161174 Field-effect transistors having doped aluminum oxide dielectrics
‌
US Patent 7161183 Liquid crystal display and method of manufacturing the same
‌
US Patent 7161222 Semiconductor device and semiconductor device fabrication method
‌
US Patent 7161245 Electronic component-mounted structure, method for mounting electronic component, electro-optical device, and electronic apparatus
‌
US Patent 7161249 Multi-chip package (MCP) with spacer
‌
US Patent 7161685 Method for measuring the distance of an object
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US Patent 7163884 Semiconductor device and fabrication method thereof
‌
US Patent 7163902 Infra-red light-emitting device and method for preparing the same
‌
US Patent 7164152 Laser-irradiated thin films having variable thickness
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US Patent 7164190 Field effect transistor
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US Patent 7166489 Complementary metal oxide semiconductor image sensor and method for fabricating the same
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US Patent 7166545 Production method for semiconductor device
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US Patent 7166921 Aluminum alloy film for wiring and sputter target material for forming the film
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US Patent 7169627 Method for inspecting a connecting surface of a flip chip
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US Patent 7169649 Wafer scale integration of electroplated 3D structures using successive lithography, electroplated sacrificial layers, and flip-chip bonding
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US Patent 7169671 Method of recording information in nonvolatile semiconductor memory
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US Patent 7169678 Method of forming a semiconductor device using a silicide etching mask
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US Patent 7169696 Method for making a system for selecting one wire from a plurality of wires
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US Patent 7170126 Structure of vertical strained silicon devices
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US Patent 7170138 Semiconductor device
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US Patent 7170146 TFT structure and method for manufacturing the same
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US Patent 7170153 Semiconductor device and its manufacturing method
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US Patent 7170171 Support ring for use with a contact pad and semiconductor device components including the same
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US Patent 7172908 Magnetic memory cells and manufacturing methods
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US Patent 7172913 Thin film transistor array panel and manufacturing method thereof
‌
US Patent 7172945 Method of manufacturing thin film capacitor
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US Patent 7172948 Method to avoid a laser marked area step height
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US Patent 7172978 MEMS device polymer film deposition process
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US Patent 7173273 Semiconductor laser device
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US Patent 7173277 Semiconductor light emitting device and method for fabricating the same
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US Patent 7173278 Thin-film transistor in which fluctuations in current flowing therethrough are suppressed, and image display apparatus
‌
US Patent 7176145 Manufacturing method of semiconductor device
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US Patent 7176563 Electronically grounded heat spreader
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US Patent 7176572 Semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
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US Patent 7179727 Formation of lattice-tuning semiconductor substrates
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US Patent 7179729 Heat treatment apparatus and method of manufacturing a semiconductor device
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US Patent 7180167 Low profile stacking system and method
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US Patent 7183131 Process for producing a nanoelement arrangement, and nanoelement arrangement
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US Patent 7183146 Method of manufacturing semiconductor device
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US Patent 7183167 Semiconductor device having a trench isolation and method of fabricating the same
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US Patent 7183198 Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes
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US Patent 7183205 Method of pitch dimension shrinkage
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US Patent 7183626 Passivation structure with voltage equalizing loops
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US Patent 7183636 Adapter for a chip card having a reduced format in comparison with the standard SIM mini-card format
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US Patent 7186571 Method of fabricating a compositionally modulated electrode in a magnetic tunnel junction device
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US Patent 7186572 Simplified bottom electrode-barrier structure for making a ferroelectric capacitor stacked on a contact plug
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US Patent 7186587 Singulation method used in image sensor packaging process and support for use therein
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US Patent 7186655 Method for manufacturing semiconductor device
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US Patent 7187048 Semiconductor light-receiving device
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US Patent 7189585 Display panel, display panel inspection method, and display panel manufacturing method
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US Patent 7189593 Elimination of RDL using tape base flip chip on flex for die stacking
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US Patent 7189601 System and method for forming mold caps over integrated circuit devices
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US Patent 7189632 Multifunctional metallic bonding
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US Patent 7190013 ISFET using PbTiO
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US Patent 7192799 Matrix type piezoelectric/electrostrictive device and manufacturing method thereof
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US Patent 7192871 Semiconductor device with a line and method of fabrication thereof
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US Patent 7192875 Processes for treating morphologically-modified silicon electrode surfaces using gas-phase interhalogens
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US Patent 7193239 Three dimensional structure integrated circuit
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US Patent 7193289 Damascene copper wiring image sensor
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US Patent 7193330 Semiconductor device with improved design freedom of external terminal
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US Patent 7195946 Process for fabricating a semiconductor device having a suspended micro-system and resultant device
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US Patent 7195988 Semiconductor wafer and method of manufacturing a semiconductor device using a separation portion on a peripheral area of the semiconductor wafer
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US Patent 7196360 Light emitting device
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US Patent 7196372 Flash memory device
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US Patent 7199024 Method of manufacturing a semiconductor device
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US Patent 7199031 Semiconductor system having a pn transition and method for manufacturing a semiconductor system
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US Patent 7202187 Method of forming sidewall spacer using dual-frequency plasma enhanced CVD
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US Patent 7202555 Pitch change and chip scale stacking system and method
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US Patent 7205178 Land grid array packaged device and method of forming same
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US Patent 7205198 Method of making a bi-directional read/program non-volatile floating gate memory cell
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US Patent 7205621 Surface shape recognition sensor
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US Patent 7205665 Porous silicon undercut etching deterrent masks and related methods
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US Patent 7208375 Semiconductor device
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US Patent 7208406 Method for forming gate in semiconductor device
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US Patent 7208797 Semiconductor device
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US Patent 7211459 Fabrication method of an ion sensitive field effect transistor
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US Patent 7212279 Biometric identity verifiers and methods
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US Patent 7214555 Method for producing display device
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US Patent 7214591 Method of fabricating high-voltage MOS device
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US Patent 7214996 Optical semiconductor housing with transparent chip and method for making same
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US Patent 7215003 Driver for driving a load using a charge pump circuit
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US Patent 7217609 Semiconductor fabrication process, lateral PNP transistor, and integrated circuit
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US Patent 7217625 Method of fabricating a semiconductor device having a shallow source/drain region
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US Patent 7217968 Recessed gate for an image sensor
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US Patent 7217975 Lateral type semiconductor device
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US Patent 7218006 Multi-chip stack package
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US Patent 7220630 Method for selectively forming strained etch stop layers to improve FET charge carrier mobility
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US Patent 7220643 System and method for gate formation in a semiconductor device
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US Patent 7220672 Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same
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US Patent 7221036 BJT with ESD self protection
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US Patent 7223692 Multi-level semiconductor device with capping layer for improved adhesion
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US Patent 7226808 Method of manufacturing semiconductor device and method of manufacturing electronics device
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US Patent 7226861 Methods and apparatus for forming rhodium-containing layers
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US Patent 7226876 Method of modifying interlayer adhesion
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US Patent 7229850 Method of making assemblies having stacked semiconductor chips
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US Patent 7229880 Precision creation of inter-gates insulator
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US Patent 7232739 Multifunctional metallic bonding
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US Patent 7233026 Light extraction from color changing medium layers in organic light emitting diode devices
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US Patent 7233061 Interposer for impedance matching
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US Patent 7235461 Method for bonding semiconductor structures together
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US Patent 7235463 Method for fabricating an electrical insulator
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US Patent 7235466 Method of fabricating a polysilicon layer
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US Patent 7235470 Semiconductor device and manufacturing method thereof
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US Patent 7235498 Process for growing a dielectric layer on a silicon-containing surface using a mixture of N
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US Patent 7238597 Boron ion delivery system
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US Patent 7238624 System and method for manufacturing semiconductor devices using a vacuum chamber
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US Patent 7239016 Semiconductor device having heat radiation plate and bonding member
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US Patent 7241655 Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
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US Patent 7241669 Method of forming a scribe line on a passive electronic component substrate
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US Patent 7241671 CMOS image sensor and method for fabricating the same
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US Patent 7241683 Stabilized photoresist structure for etching process
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US Patent 7244641 Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device
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US Patent 7244644 Undercut and residual spacer prevention for dual stressed layers
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US Patent 7245028 Split control pad for multiple signal
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US Patent 7247503 Method of laser annealing to form an epitaxial growth layer
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US Patent 7247551 Substrate for electronic device, method for manufacturing substrate for electronic device, and electronic device
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US Patent 7247556 Control of wafer warpage during backend processing
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US Patent 7247567 Method of polishing a tungsten-containing substrate
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US Patent 7247579 Cleaning methods for silicon electrode assembly surface contamination removal
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US Patent 7247928 Semiconductor device with electrical connection balls between an integrated circuit chip and a support plate, and process for fabricating it
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US Patent 7250333 Method of fabricating a linearized output driver and terminator
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US Patent 7250337 Method for fabricating a nonvolatile sonos memory device
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US Patent 7250342 Method of fabricating a MOSFET having a recessed channel
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US Patent 7250373 Method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate
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US Patent 7250672 Dual semiconductor die package with reverse lead form
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US Patent 7250680 Semiconductor circuitry constructions
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US Patent 7253048 Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit
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US Patent 7253057 Memory cell with reduced size and standby current
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US Patent 7256062 Semiconductor photo-detector, semiconductor photo-detection device, and production methods thereof
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US Patent 7256079 Evaluation method using a TEG, a method of manufacturing a semiconductor device having a TEG, an element substrate and a panel having the TEG, a program for controlling dosage and a computer-readable recording medium recoding the program
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US Patent 7256100 Manufacturing method of semiconductor device having trench type element isolation
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US Patent 7256440 Semiconductor memory cell having a trench and a planar selection transistor and method for producing the same
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US Patent 7256502 Metal interconnections for semiconductor devices including a buffer layer on a trench sidewall
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US Patent 7259060 Method for fabricating a semiconductor structure
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US Patent 7259072 Shallow low energy ion implantation into pad oxide for improving threshold voltage stability
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US Patent 7259078 Method for forming isolation layer in semiconductor memory device
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US Patent 7262067 Method for conductive film quality evaluation
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US Patent 7262132 Metal plating using seed film
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US Patent 7262465 P-channel MOS transistor and fabrication process thereof
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US Patent 7264974 Method for fabricating a low resistance TMR read head
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US Patent 7265010 High performance vertical PNP transistor method
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US Patent 7265026 Method of forming a shallow trench isolation structure in a semiconductor device
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US Patent 7265063 Method of forming a component having dielectric sub-layers
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US Patent 7265406 Capacitor with conducting nanostructure
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US Patent 7268045 N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects
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US Patent 7271034 Semiconductor device with a high thermal dissipation efficiency
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US Patent 7271054 Method of manufacturing a ferroelectric capacitor having RU1-XOX electrode
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US Patent 7271481 Microelectronic component and assembly having leads with offset portions
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US Patent 7271496 Integrated circuit package-in-package system
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US Patent 7273798 Gallium nitride device substrate containing a lattice parameter altering element
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US Patent 7279376 Method for manufacturing semiconductor device
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US Patent 7279387 Method for fabricating asymmetric semiconductor device
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US Patent 7279400 Method of fabricating single-layer and multi-layer single crystalline silicon and silicon devices on plastic using sacrificial glass
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US Patent 7279416 Methods of forming a conductive structure in an integrated circuit device
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US Patent 7282131 Methods of electrochemically treating semiconductor substrates
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US Patent 7282436 Plasma treatment for silicon-based dielectrics
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US Patent 7282740 Semiconductor light emitting device
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US Patent 7285466 Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels
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US Patent 7285485 Method for forming a gate in a semiconductor, which prevents gate leaning caused by thermal processing
‌
US Patent 7285837 Electrostatic discharge device integrated with pad
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US Patent 7288439 Leadless microelectronic package and a method to maximize the die size in the package
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US Patent 7288468 Luminescent efficiency of semiconductor nanocrystals by surface treatment
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US Patent 7288816 Semiconductor device
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US Patent 7288826 Semiconductor integrated circuit device
‌
US Patent 7288829 Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide
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US Patent 7291553 Method for forming dual damascene with improved etch profiles
‌
US Patent 7291557 Method for forming an interconnection structure for ic metallization
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US Patent 7291862 Thin film transistor substrate and production method thereof
‌
US Patent 7294520 Method for fabricating a plurality of semiconductor bodies, and electronic semiconductor body
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US Patent 7294551 Semiconductor device and method for manufacturing the same
‌
US Patent 7297602 Conductive metal oxide gate ferroelectric memory transistor
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US Patent 7300828 Method of manufacturing a liquid crystal display device
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US Patent 7301205 Semiconductor device and method of manufacturing the same
‌
US Patent 7301225 Multi-row lead frame
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US Patent 7303927 Three-dimensional ferroelectric capacitor and method for manufacturing thereof as well as semiconductor memory device
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US Patent 7303933 Process of manufacturing a semiconductor device
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US Patent 7303951 Method of manufacturing a trench isolation region in a semiconductor device
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US Patent 7304350 Threshold voltage control layer in a semiconductor device
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US Patent 7306985 Method for manufacturing semiconductor device including heat treating with a flash lamp
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US Patent 7307281 Method of manufacturing substrate, method of manufacturing organic electroluminescent display device using the method, and organic electroluminescent display device
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US Patent 7309636 High-voltage metal-oxide-semiconductor device and method of manufacturing the same
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US Patent 7309897 Electrostatic discharge protector for an integrated circuit
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US Patent 7309901 Field effect transistors (FETs) with multiple and/or staircase silicide
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US Patent 7312139 Method of fabricating nitrogen-containing gate dielectric layer and semiconductor device
‌
US Patent 7316971 Wire bond pads
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US Patent 7320913 Methods of forming split-gate non-volatile memory devices
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US Patent 7321141 Image sensor device and manufacturing method thereof
‌
US Patent 7321170 High frequency semiconductor device
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US Patent 7323381 Semiconductor device and manufacturing method thereof
‌
US Patent 7323383 Method for fabricating an NROM memory cell arrangement
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US Patent 7323412 Atomic layer deposition methods, and methods of forming materials over semiconductor substrates
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US Patent 7323759 Photosensor for a transmitted light method used for detecting the direction of movement of intensity maxima and intensity minima of an optical standing wave
‌
US Patent 7323780 Electrical interconnection structure formation
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US Patent 7326624 Method of making thin-film chip resistor
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US Patent 7326960 Semiconductor circuit constructions
‌
US Patent 7327448 Laser-ultrasonic detection of flip chip attachment defects
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US Patent 7329585 Method of manufacturing semiconductor device
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US Patent 7329586 Gapfill using deposition-etch sequence
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US Patent 7329607 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
‌
US Patent 7329614 Heat resistant ohmic electrode and method of manufacturing the same
‌
US Patent 7332379 Method of an array of structures sensitive to ESD and structure made therefrom
‌
US Patent 7332388 Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same
‌
US Patent 7332409 Methods of forming trench isolation layers using high density plasma chemical vapor deposition
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US Patent 7332416 Methods to manufacture contaminant-gettering materials in the surface of EUV optics
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US Patent 7332426 Substrate processing method and fabrication process of a semiconductor device
‌
US Patent 7332427 Method of forming an interconnection line in a semiconductor device
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US Patent 7332428 Metal interconnect structure and method
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US Patent 7332749 Junction-gate type static induction thyristor and high-voltage pulse generator using such junction-gate type static induction thyristor
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US Patent 7335578 Method for manufacturing semiconductor chip
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US Patent 7335591 Method for forming three-dimensional structures on a substrate
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US Patent 7335606 Silicide formed from ternary metal alloy films
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US Patent 7335947 Angled implant for shorter trench emitter
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US Patent 7335971 Method for protecting encapsulated sensor structures using stack packaging
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US Patent 7338820 Laser patterning of encapsulated organic light emitting diodes
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US Patent 7338822 LED fabrication via ion implant isolation
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US Patent 7338865 Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation
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US Patent 7338878 Method for forming capacitor in semiconductor device
‌
US Patent 7338879 Method of fabricating a semiconductor device having dual stacked MIM capacitor
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US Patent 7339193 Dual panel-type organic electroluminescent display device and method of fabricating the same
‌
US Patent 7339199 Semiconductor package including light emitter and IC
‌
US Patent 7339211 Semiconductor device and method for fabricating the same
‌
US Patent 7339267 Semiconductor package and method for forming the same
‌
US Patent 7342261 Light emitting device
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US Patent 7342268 CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom
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US Patent 7342303 Semiconductor device having RF shielding and method therefor
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US Patent 7344913 Spin on memory cell active layer doped with metal ions
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US Patent 7344935 Method of manufacturing a semiconductor integrated circuit device
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US Patent 7344945 Method of manufacturing a drain side gate trench metal-oxide-semiconductor field effect transistor
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US Patent 7345316 Wafer level packaging for optoelectronic devices
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US Patent 7345344 Embedded substrate interconnect for underside contact to source and drain regions
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US Patent 7345355 Complementary junction-narrowing implants for ultra-shallow junctions
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US Patent 7345363 Semiconductor device with a rewiring level and method for producing the same
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US Patent 7348268 Controlled breakdown phase change memory device
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US Patent 7348601 Nitride-based compound semiconductor light emitting device
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US Patent 7348610 Multiple layer and crystal plane orientation semiconductor substrate
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US Patent 7348622 Memories having a charge storage node at least partially located in a trench in a semiconductor substrate and electrically coupled to a source/drain region formed in the substrate
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US Patent 7348658 Multilayer silicon over insulator device
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US Patent 7348681 Electronic component and manufacturing method of the electronic component
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US Patent 7351614 Deep trench isolation for thyristor-based semiconductor device
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US Patent 7351626 Method for controlling defects in gate dielectrics
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US Patent 7352023 Constructions comprising hafnium oxide
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US Patent 7352454 Methods and devices for improved charge management for three-dimensional and color sensing
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US Patent 7354779 Topography compensated film application methods
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US Patent 7354826 Method for forming memory array bitlines comprising epitaxially grown silicon and related structure
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US Patent 7355203 Use of gate electrode workfunction to improve DRAM refresh
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US Patent 7355206 Thin film transistor array panel and manufacturing method thereof
‌
US Patent 7355249 Silicon-on-insulator based radiation detection device and method
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US Patent 7355254 Pinning layer for low resistivity N-type source drain ohmic contacts
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US Patent 7355291 Overlay marks, methods of overlay mark design and methods of overlay measurements
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US Patent 7358151 Microelectromechanical system microphone fabrication including signal processing circuitry on common substrate
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US Patent 7358184 Method of forming a conductive via plug
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US Patent 7358553 System and method for reducing shorting in memory cells
‌
US Patent 7358563 CMOS image sensor and method for fabricating the same
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US Patent 7358583 Via wave guide with curved light concentrator for image sensing devices
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US Patent 7358604 Multichip circuit module and method for the production thereof
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US Patent 7361543 Method of forming a nanocluster charge storage device
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US Patent 7361544 Method for fabricating capacitor in semiconductor device
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US Patent 7361571 Method for fabricating a trench isolation with spacers
‌
US Patent 7361952 Semiconductor apparatus and method of manufacturing the same
‌
US Patent 11183395 Semiconductor device and fabrication method thereof
‌
US Patent 11183406 Control of wafer bow in multiple stations
‌
US Patent 11183455 Interconnects with enlarged contact area
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US Patent 11183534 Light emitting device with small footprint
‌
US Patent 11183650 Display substrate, method of manufacturing the same, and display device including the same
‌
US Patent 7364784 Thin semiconductor package having stackable lead frame and method of manufacturing the same
‌
US Patent 7364961 SRAM cell design for soft error rate immunity
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US Patent 7364996 Methods of fabricating patterned layers on a substrate
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US Patent 7365381 Optical sensor with improved planarization
‌
US Patent 7365391 Semiconductor device and method for manufacturing thereof
‌
US Patent 7365434 Semiconductor device and manufacturing method for the same
‌
US Patent 7365441 Semiconductor device fabricating apparatus and semiconductor device fabricating method
‌
US Patent 7365825 Liquid crystal display device including repair pattern and method for fabricating the same
‌
US Patent 7368299 MTJ patterning using free layer wet etching and lift off techniques
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US Patent 7368345 Flash memory devices and methods of fabricating the same
‌
US Patent 7368767 Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential
‌
US Patent 7368780 Semiconductor memory device and method of manufacturing the same
‌
US Patent 7368782 Dual-bit non-volatile memory cell and method of making the same
‌
US Patent 7368794 Boron carbide particle detectors
‌
US Patent 7371609 Stacked module systems and methods
‌
US Patent 7371623 Semiconductor device with semiconductor circuit comprising semiconductor units, and method for fabricating it
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US Patent 7371638 Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same
‌
US Patent 7371653 Metal interconnection structure of semiconductor device and method of forming the same
‌
US Patent 7372080 Gan semiconductor device
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US Patent 7372108 Semiconductor device and manufacturing method thereof
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US Patent 7372115 Thermally isolated membrane structure
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US Patent 7372137 Semiconductor device and manufacturing method thereof
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US Patent 7374981 Thin film transistor, electronic device having the same, and method for manufacturing the same
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US Patent 7374990 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
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US Patent 7374994 Bismuth titanium silicon oxide, bismuth titanium silicon oxide thin film, and method for forming the thin film
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US Patent 7375001 Semiconductor device and method therefore
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US Patent 7375009 Method of forming a conductive via through a wafer
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US Patent 7375413 Trench widening without merging
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US Patent 7375431 Solder bump formation in electronics packaging
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US Patent 7378299 Leadless semiconductor package and manufacturing method thereof
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US Patent 7378329 Method for manufacturing semiconductor device
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US Patent 7378706 Semiconductor device and method of manufacturing the same
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US Patent 7384817 Method of assembling semiconductor devices with LEDs
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US Patent 7390740 Sloped vias in a substrate, spring-like contacts, and methods of making
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US Patent 7390758 Method of manufacturing a semiconductor integrated circuit device with elimination of static charge
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US Patent 7391047 System for forming a strained layer of semiconductor material
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US Patent 7391116 Fretting and whisker resistant coating system and method
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US Patent 7393743 Methods of forming a plurality of capacitors
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US Patent 7397062 Heterojunction bipolar transistor with improved current gain
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US Patent 7400040 Thermal interface apparatus, systems, and methods
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US Patent 7402480 Method of fabricating a semiconductor device with multiple gate oxide thicknesses
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US Patent 7416947 Method of fabricating trench MIS device with thick oxide layer in bottom of trench
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US Patent 7416969 Void free solder arrangement for screen printing semiconductor wafers
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US Patent 7417315 Negative thermal expansion system (NTEs) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging
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US Patent 7419901 Semiconductor device and a method of manufacturing the same
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US Patent 7422930 Integrated circuit with re-route layer and stacked die assembly
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US Patent 7446026 Method of forming a CMOS device with stressor source/drain regions
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US Patent 7449404 Method for improving Mg doping during group-III nitride MOCVD
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US Patent 7449732 Substrate with transparent electrodes and devices incorporating it
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US Patent 7459761 High performance system-on-chip using post passivation process
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US Patent 7465661 High aspect ratio microelectrode arrays
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US Patent 7473937 Side-emission type LED package
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US Patent 7473940 Compact LED with a self-formed encapsulating dome
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US Patent 7476594 Methods of fabricating silicon nitride regions in silicon carbide and resulting structures
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US Patent 7476939 Memory cell having an electrically floating body transistor and programming technique therefor
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US Patent 7479415 Fabrication method of polycrystalline silicon liquid crystal display device
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US Patent 7479422 Semiconductor device with stressors and method therefor
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US Patent 7485571 Method of making an integrated circuit
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US Patent 7485909 Semiconductor device and method of manufacturing the same
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US Patent 7485961 Approach to avoid buckling in BPSG by using an intermediate barrier layer
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US Patent 7488970 Semiconductor device
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US Patent 7492032 Fuse regions of a semiconductor memory device and methods of fabricating the same
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US Patent 7498201 Method of forming a multi-die semiconductor package
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US Patent 7498269 Cleaning methods for silicon electrode assembly surface contamination removal
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US Patent 7501327 Fabricating method of semiconductor optical device for flip-chip bonding
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US Patent 7504729 Semiconductor device with extraction electrode
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US Patent 7507621 Method of manufacturing semiconductor device
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US Patent 7510908 Method to dispense light blocking material for wafer level CSP
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US Patent 7510975 Method for manufacturing a semiconductor device having trenches defined in the substrate surface
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US Patent 11189505 Substrate liquid processing apparatus, substrate liquid processing method and storage medium
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US Patent 7517773 Method of manufacturing a thin film transistor
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US Patent 7517795 Stabilization of Ni monosilicide thin films in CMOS devices using implantation of ions before silicidation
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US Patent 7521351 Method for forming a semiconductor product and semiconductor product
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US Patent 7524740 Localized strain relaxation for strained Si directly on insulator
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US Patent 7528044 CMOSFET with hybrid-strained channels
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US Patent 7528068 Method for manufacturing semiconductor device
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US Patent 7531404 Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer
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US Patent 7547646 Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates
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US Patent 7550325 Method of manufacturing an active matrix display device
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US Patent 7550377 Method for fabricating single-damascene structure, dual damascene structure, and opening thereof
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US Patent 7566603 Method for manufacturing semiconductor device having metal silicide layer
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US Patent 7569877 System and method based on field-effect transistors for addressing nanometer-scale devices
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US Patent 7579646 Flash memory with deep quantum well and high-K dielectric
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US Patent 7598121 Method of manufacturing a semiconductor device
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US Patent 7601628 Wire and solder bond forming methods
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US Patent 7601652 Method for treating substrates and films with photoexcitation
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US Patent 7602030 Hafnium tantalum oxide dielectrics
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US Patent 7615859 Thin semiconductor package having stackable lead frame and method of manufacturing the same
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US Patent 7619256 Electro-optical device and electronic apparatus
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US Patent 7663239 Semiconductor device and method for fabricating the same
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US Patent 7696517 NMOS transistors that mitigate fermi-level pinning by employing a hafnium-silicon gate electrode and high-k gate dieletric
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US Patent 7781837 Stacked film including a semiconductor film having a taper angle, and thin film transistor including the stacked film
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US Patent 7825527 Return loss techniques in wirebond packages for high-speed data communications
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US Patent RE41989 Method and apparatus for electronic device manufacture using shadow masks
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US Patent 7846755 Light emitting diode having plurality of light emitting cells and method of fabricating the same
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US Patent RE42004 Method for fabricating a semiconductor storage device having an increased dielectric film area
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US Patent 7863648 Field effect transistor
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US Patent 7879636 Method of forming p-type gallium nitride based semiconductor, method of forming nitride semiconductor device, and method of forming epitaxial wafer
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US Patent 7923323 Metal capacitor including lower metal electrode having hemispherical metal grains
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US Patent 7932130 Method for forming an etched recess package on package system
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US Patent 7969805 Coupling methods and architectures for information processing
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US Patent 7994572 MOSFET having recessed channel
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US Patent 7998796 Semiconductor device and manufacturing method thereof
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US Patent 7998796 Semiconductor device and manufacturing method thereof
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US Patent 7994572 MOSFET having recessed channel
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US Patent 7969805 Coupling methods and architectures for information processing
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edited on 7 Dec, 2021
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US Patent 7932130 Method for forming an etched recess package on package system
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US Patent 7923323 Metal capacitor including lower metal electrode having hemispherical metal grains
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US Patent RE41989 Method and apparatus for electronic device manufacture using shadow masks
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US Patent 7825527 Return loss techniques in wirebond packages for high-speed data communications
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US Patent 7663239 Semiconductor device and method for fabricating the same
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US Patent 7619256 Electro-optical device and electronic apparatus
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US Patent 7601652 Method for treating substrates and films with photoexcitation

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