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Michael Lebentritt

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Calvin Brooks
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Golden AI
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Patent primary examiner of
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US Patent 11168698 Ceiling fan
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US Patent 7087439 Method and apparatus for thermally assisted testing of integrated circuits
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US Patent 7087469 Method of controlling a capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor
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US Patent 7087495 Method for manufacturing semiconductor device
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US Patent 7091110 Method of manufacturing a semiconductor device by gettering using a anti-diffusion layer
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US Patent 7091112 Method of forming a polycrystalline silicon layer
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US Patent 7091118 Replacement metal gate transistor with metal-rich silicon layer and method for making the same
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US Patent 7091133 Two-step formation of etch stop layer
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US Patent 7092077 System and method for monitoring contamination
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US Patent 7094670 Plasma immersion ion implantation process
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US Patent 7094678 Electrostatic discharge protection of thin-film resonators
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US Patent 7098071 Method for flip chip bonding by utilizing an interposer with embedded bumps
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US Patent 7098124 Method of forming contact hole and method of fabricating semiconductor device
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US Patent 7098146 Semiconductor device having patterned SOI structure and method for fabricating the same
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US Patent 7101729 Method of manufacturing a semiconductor device having adjoining substrates
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US Patent 7101733 Leadframe with a chip pad for two-sided stacking and method for manufacturing the same
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US Patent 7101739 Method for forming a schottky diode on a silicon carbide substrate
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US Patent 7101770 Capacitive techniques to reduce noise in high speed interconnections
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US Patent 7101793 Power module and its manufacturing method
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US Patent 7105360 Low temperature melt-processing of organic-inorganic hybrid
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US Patent 7105457 Semiconductor device manufacturing method and apparatus used in the semiconductor device manufacturing method
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US Patent 7105916 Inlet for an electronic tag
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US Patent 7109060 Manufacturing method of semiconductor device, semiconductor device, circuit substrate and electronic equipment
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US Patent 7109115 Methods of providing ohmic contact
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US Patent 7109124 Solid state plasma antenna
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US Patent 7112475 Method of fabricating a thin film transistor with multiple gates using metal induced lateral crystallization
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US Patent 7112489 Negative resist or dry develop process for forming middle of line implant layer
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US Patent 7112509 Method of producing a high resistivity SIMOX silicon substrate
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US Patent 7112511 CMOS image sensor having prism and method for fabricating the same
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US Patent 7115424 Method for manufacturing semiconductor device
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US Patent 7115446 Flip chip bonding method for enhancing adhesion force in flip chip packaging process and metal layer-built structure of substrate for the same
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US Patent 7115449 Method for fabrication of polycrystalline silicon thin film transistors
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US Patent 7115456 Sequential lateral solidification device and method of crystallizing silicon using the same
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US Patent 7115505 Methods for electrically isolating portions of wafers
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US Patent 7118953 Process of fabricating termination region for trench MIS device
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US Patent 7118956 Trench capacitor and a method for manufacturing the same
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US Patent 7118969 Method of manufacturing a floating gate and method of manufacturing a non-volatile semiconductor memory device comprising the same
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US Patent 7119002 Solder bump composition for flip chip
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US Patent 7119005 Semiconductor local interconnect and contact
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US Patent 7119011 Semiconductor device and manufacturing method thereof
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US Patent 7119030 Process for lining a surface using an organic film
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US Patent 7119362 Method of manufacturing semiconductor apparatus
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US Patent 7119403 High performance strained CMOS devices
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US Patent 7122396 Semiconductor acceleration sensor and process for manufacturing the same
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US Patent 7122420 Methods of recessing conductive material and methods of forming capacitor constructions
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US Patent 7122439 Method of fabricating a bottle trench and a bottle trench capacitor
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US Patent 7122461 Method to assemble structures from nano-materials
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US Patent 7122464 Systems and methods of forming refractory metal nitride layers using disilazanes
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US Patent 7122484 Process for removing organic materials during formation of a metal interconnect
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US Patent 7125754 Semiconductor device and its manufacturing method
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US Patent 7125764 Method of producing solid electrolytic capacitor
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US Patent 7125774 Method of manufacturing transistor having recessed channel
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US Patent 7129100 In-wafer testing of integrated optical components in photonic integrated circuits (PICs)
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US Patent 7129105 Method for manufacturing thin film transistor array panel for display device
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US Patent 7129106 Thin film transistor substrate of a horizontal electric field type and method of darkening defective pixel in the same
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US Patent 7129112 Manufacturing method for semiconductor device, semiconductor device, and electronic apparatus
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US Patent 7129140 Method of forming polysilicon gate structures with specific edge profiles for optimization of LDD offset spacing
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US Patent 7129147 Delivery position aligning method for use in a transfer system and a processing system employing the method
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US Patent 7129188 Transistor fabrication methods
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US Patent 7129519 Monitoring system comprising infrared thermopile detector
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US Patent 7132297 Multi-layer inductor formed in a semiconductor substrate and having a core of ferromagnetic material
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US Patent 7132301 Method and apparatus for reviewing voltage contrast defects in semiconductor wafers
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US Patent 7132322 Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device
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US Patent 7132325 Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
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US Patent 7132354 Inspection methods for a semiconductor device
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US Patent 7132358 Method of forming solder bump with reduced surface defects
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US Patent 7132360 Method for treating a semiconductor surface to form a metal-containing layer
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US Patent 7132375 Method of manufacturing a semiconductor device by crystallization of a semiconductor region by use of a continuous wave laser beam through the substrate
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US Patent 11174798 Mission adaptive clearance control system and method of operation
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US Patent 11174841 Method for increasing the yield of a wind farm under icing conditions
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US Patent 11174869 Rotary machine
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US Patent 11174876 Blower
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US Patent 11177173 Semiconductor device with an interconnect structure and method for forming the same
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US Patent 11177489 Centrifugal compressor with diffuser
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US Patent 7135354 Semiconductor device and method of manufacturing the same, semiconductor wafer, circuit board and electronic instrument
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US Patent 7135367 Manufacturing method of semiconductor device
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US Patent 7135375 Varactors for CMOS and BiCMOS technologies
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US Patent 7135382 In-wafer testing of integrated optical components in photonic integrated circuits (PICs)
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US Patent 7135387 Method of manufacturing semiconductor element
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US Patent 7135400 Damascene process capable of avoiding via resist poisoning
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US Patent 7135403 Method for forming metal interconnection line in semiconductor device
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US Patent 7138283 Method for analyzing fail bit maps of wafers
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US Patent 7138307 Method to produce highly doped polysilicon thin films
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US Patent 7138315 Low thermal resistance semiconductor device and method therefor
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US Patent 7138320 Advanced technique for forming a transistor having raised drain and source regions
‌
US Patent 7138322 Semiconductor device and fabrication method therefor
‌
US Patent 7141438 Magnetic tunnel junction structure having an oxidized buffer layer and method of fabricating the same
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US Patent 7141449 Method of fabricating a compound semiconductor thin-layer solar cell
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US Patent 7141472 Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry
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US Patent 7141493 Semiconductor device, method of manufacturing three-dimensional stacking type semiconductor device, circuit board, and electronic instrument
‌
US Patent 7141494 Method for reducing tungsten film roughness and improving step coverage
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US Patent 7141515 Method for manufacturing device
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US Patent 7144756 Structure and material for assembling a low-K Si die to achieve a low warpage and industrial grade reliability flip chip package with organic substrate
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US Patent 7144773 Method for preventing trenching in fabricating split gate flash devices
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US Patent 7144784 Method of forming a semiconductor device and structure thereof
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US Patent 7144788 Method for manufacturing a transmitting optical sub-assembly with a thermo-electric cooler therein
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US Patent 7144791 Lamination through a mask
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US Patent 7144797 Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same
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US Patent 7144808 Integration flow to prevent delamination from copper
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US Patent 7148090 Method of fabricating a TFT device formed by printing
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US Patent 7148103 Multilevel poly-Si tiling for semiconductor circuit manufacture
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US Patent 7148108 Method of manufacturing semiconductor device having step gate
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US Patent 7148112 Method for manufacturing semiconductor device including a recess channel
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US Patent 7148117 Methods for forming shallow trench isolation structures in semiconductor devices
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US Patent 7148126 Semiconductor device manufacturing method and ring-shaped reinforcing member
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US Patent 7148137 Method of forming metal line in semiconductor device
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US Patent 7148141 Method for manufacturing metal structure having different heights
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US Patent 7148143 Semiconductor device having a fully silicided gate electrode and method of manufacture therefor
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US Patent 7151003 Semiconductor wafer test system
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US Patent 7151010 Methods for assembling a stack package for high density integrated circuits
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US Patent 7151016 Method of manufacturing a semiconductor device that includes a hydrogen concentration depth profile
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US Patent 7151023 Metal gate MOSFET by full semiconductor metal alloy conversion
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US Patent 7151035 Semiconductor device and manufacturing method thereof
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US Patent 7151052 Multiple etch-stop layer deposition scheme and materials
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US Patent 7151060 Device and method for thermally treating semiconductor wafers
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US Patent 7153721 Resistance variable memory elements based on polarized silver-selenide network growth
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US Patent 7153722 Method and apparatus for manufacturing photovoltaic device
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US Patent 7153730 Pulse width method for controlling lateral growth in crystallized silicon films
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US Patent 7153731 Method of forming a field effect transistor with halo implant regions
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US Patent 7153735 Method of manufacturing semiconductor device
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US Patent 7153745 Recessed gate transistor structure and method of forming the same
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US Patent 7153768 Backside coating for MEMS wafer
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US Patent 7157292 Leadframe for a multi-chip package and method for manufacturing the same
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US Patent 7157309 Manufacture of microelectronic fold packages
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US Patent 7157321 Semiconductor device and method for manufacturing the same
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US Patent 7157328 Selective etching to increase trench surface area
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US Patent 7157331 Ultraviolet blocking layer
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US Patent 7157337 Method of manufacturing a semiconductor device and semiconductor device obtained by means of such a method
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US Patent 7157340 Method of fabrication of semiconductor device
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US Patent 7157368 Method of accelerating test of semiconductor device
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US Patent 7157383 Method for forming silicon dioxide film on silicon substrate, method for forming oxide film on semiconductor substrate, and method for producing semiconductor device
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US Patent 7160772 Structure and method for integrating MIM capacitor in BEOL wiring levels
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US Patent 7160819 Method to perform selective atomic layer deposition of zinc oxide
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US Patent 7163839 Multi-chip module and method of manufacture
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US Patent 7163841 Method of manufacturing circuit device
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US Patent 7163849 Fabrication method of semiconductor integrated circuit device
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US Patent 7163856 Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor
‌
US Patent 7163868 Method for forming a lightly doped drain in a thin film transistor
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US Patent 7163869 Shallow trench isolation structure with converted liner layer
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US Patent 7163883 Edge seal for a semiconductor device
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US Patent 7166496 Method of making a packaged semiconductor device
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US Patent 7166505 Method for making a semiconductor device having a high-k gate dielectric
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US Patent 7166506 Poly open polish process
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US Patent 7166507 Semiconductor device and method for forming same using multi-layered hard mask
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US Patent 7166510 Method for manufacturing flash memory device
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US Patent 7166519 Method for isolating semiconductor devices with use of shallow trench isolation method
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US Patent 7166531 VLSI fabrication processes for introducing pores into dielectric materials
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US Patent 7166537 Miniaturized imaging device with integrated circuit connector system
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US Patent 7166540 Method for reducing assembly-induced stress in a semiconductor die
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US Patent 7166542 Method for fabricating passivation layer
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US Patent 7169195 Capacitor, circuit board with built-in capacitor and method of manufacturing the same
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US Patent 7169625 Method for automatic determination of semiconductor plasma chamber matching and source of fault by comprehensive plasma monitoring
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US Patent 7169658 Method for formation of an ultra-thin film and semiconductor device containing such a film
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US Patent 7169673 Atomic layer deposited nanolaminates of HfO
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US Patent 7169674 Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier
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US Patent 7169676 Semiconductor devices and methods for forming the same including contacting gate to source
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US Patent 7169677 Method for producing a spacer structure
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US Patent 7169685 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
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US Patent 7169698 Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner
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US Patent 7169704 Method of cleaning a surface of a water in connection with forming a barrier layer of a semiconductor device
‌
US Patent 7169705 Plating method and plating apparatus
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US Patent 7172918 Infrared thermopile detector system for semiconductor process monitoring and control
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US Patent 7172933 Recessed polysilicon gate structure for a strained silicon MOSFET device
‌
US Patent 7172960 Multi-layer film stack for extinction of substrate reflections during patterning
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US Patent 7172962 Method of manufacturing a semiconductor device
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US Patent 7176042 Laser beam irradiation method that includes determining a thickness of semiconductor prior to crystallizing
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US Patent 7176044 B-stageable die attach adhesives
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US Patent 7176084 Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory
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US Patent 7176087 Methods of forming electrical connections
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US Patent 7176096 Transistor gate and local interconnect
‌
US Patent 7176098 Semiconductor element and method for fabricating the same
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US Patent 7176110 Technique for forming transistors having raised drain and source regions with different heights
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US Patent 7176127 Method of manufacturing semiconductor device having through hole with adhesion layer thereon
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US Patent 7176129 Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
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US Patent 7176143 Method for evaluating solution for a coating film for semiconductors
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US Patent 7176536 Semiconductor device having metal silicide layer on source/drain region and gate electrode and method of manufacturing the same
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US Patent 7179665 Optical method for determining the doping depth profile in silicon
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US Patent 7179682 Packaged device and method of forming same
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US Patent 7179687 Semiconductor device and its manufacturing method, and semiconductor device manufacturing system
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US Patent 7179693 Method for manufacturing thin film device that includes a chemical etchant process
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US Patent 7179704 Methods of forming capacitors with high dielectric layers and capacitors so formed
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US Patent 7179714 Method of fabricating MOS transistor having fully silicided gate
‌
US Patent 7179722 Wafer dividing method
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US Patent 7179723 Wafer processing method
‌
US Patent 7179728 Optical component and manufacturing method thereof, microlens substrate and manufacturing method thereof, display device, and imaging device
‌
US Patent 7179734 Method for forming dual damascene pattern
‌
US Patent 7183141 Reversible field-programmable electric interconnects
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US Patent 7183143 Method for forming nitrided tunnel oxide layer
‌
US Patent 7183158 Method of fabricating a non-volatile memory
‌
US Patent 7183191 Method for fabricating a chip scale package using wafer level processing
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US Patent 7183195 Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler
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US Patent 7186586 Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
‌
US Patent 7186625 High density MIMCAP with a unit repeatable structure
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US Patent 7186628 Method of manufacturing an SOI wafer where COP's are eliminated within the base wafer
‌
US Patent 7186648 Barrier first method for single damascene trench applications
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US Patent 7187084 Damascene method employing composite etch stop layer
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US Patent 7189588 Group III nitride semiconductor substrate and its manufacturing method
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US Patent 7189623 Semiconductor processing method and field effect transistor
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US Patent 7189641 Methods of fabricating tungsten contacts with tungsten nitride barrier layers in semiconductor devices, tungsten contacts with tungsten nitride barrier layers
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US Patent 7189643 Semiconductor device and method of fabricating the same
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US Patent 7189655 Method of correcting amplitude defect in multilayer film of EUVL mask
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US Patent 7189658 Strengthening the interface between dielectric layers and barrier layers with an oxide layer of varying composition profile
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US Patent 7189664 Method for producing hydrogenated silicon-oxycarbide films
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US Patent 7192789 Method for monitoring an ion implanter
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US Patent 7192834 LDMOS device and method of fabrication of LDMOS device
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US Patent 7192840 Semiconductor device fabrication method using oxygen ion implantation
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US Patent 7192841 Method of wafer/substrate bonding
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US Patent 7192852 Method for fabricating image display device
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US Patent 7192853 Method of improving the breakdown voltage of a diffused semiconductor junction
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US Patent 7192857 Method of forming a semiconductor structure with non-uniform metal widths
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US Patent 7192885 Method for texturing surfaces of silicon wafers
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US Patent 7195928 Method of manufacturing ferroelectric substance thin film and ferroelectric memory using the ferroelectric substance thin film
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US Patent 7195937 Method for measuring withstand voltage of semiconductor epitaxial wafer and semiconductor epitaxial wafer
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US Patent 7195942 Radiation emitting semiconductor device
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US Patent 7195981 Method of forming an integrated circuit employable with a power converter
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US Patent 7195983 Programming, erasing, and reading structure for an NVM cell
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US Patent 7195990 Process for producing a photoelectric conversion device that includes using a gettering process
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US Patent 7198996 Component built-in module and method for producing the same
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US Patent 7199026 Semiconductor device, cutting equipment for cutting semiconductor device, and method for cutting the same
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US Patent 7199043 Method of forming copper wiring in semiconductor device
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US Patent 7199057 Method of eliminating boron contamination in annealed wafer
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US Patent 7201803 Valve control system for atomic layer deposition chamber
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US Patent 7202122 Cobalt silicidation process for substrates with a silicon—germanium layer
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US Patent 7202131 Method of fabricating semiconductor device
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US Patent 7205176 Surface MEMS mirrors with oxide spacers
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US Patent 7205207 High performance strained CMOS devices
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US Patent 7205208 Method of manufacturing a semiconductor device
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US Patent 7205227 Methods of forming CMOS constructions
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US Patent 7205245 Method of forming trench isolation within a semiconductor substrate
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US Patent 7208352 Method of fabricating a thin film transistor with multiple gates using metal induced lateral crystallization
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US Patent 7208357 Template layer formation
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US Patent 7208370 Method for fabricating a vertical transistor in a trench, and vertical transistor
‌
US Patent 7208394 Method of manufacturing a semiconductor device with a fluorine concentration
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US Patent 7208403 Tile-based routing method of a multi-layer circuit board and related structure
‌
US Patent 7208696 Method of forming a polycrystalline silicon layer
‌
US Patent 7211450 System and method for detection of spatial signature yield loss
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US Patent 7211451 Process for producing a component module
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US Patent 7211461 Manufacturing apparatus
‌
US Patent 7211482 Method of forming a memory cell having self-aligned contact regions
‌
US Patent 7211488 Method of forming inter-dielectric layer in semiconductor device
‌
US Patent 7211489 Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal
‌
US Patent 7211517 Semiconductor device and method that includes reverse tapering multiple layers
‌
US Patent 7214289 Method and apparatus for wall film monitoring
‌
US Patent 7214553 Process for the localized growth of nanotubes and process for fabricating a self-aligned cathode using the nanotube growth process
‌
US Patent 7214573 Method of manufacturing a semiconductor device that includes patterning sub-islands
‌
US Patent 7214598 Formation of lattice-tuning semiconductor substrates
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US Patent 7214602 Method of forming a conductive structure
‌
US Patent 7214603 Method for fabricating interconnect structures with reduced plasma damage
‌
US Patent 7214605 Deposition of diffusion barrier
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US Patent 7214610 Process for producing aluminum-filled contact holes
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US Patent 7214614 System for controlling metal formation processes using ion implantation
‌
US Patent 7214622 Manufacturing method of semiconductor device
‌
US Patent 7215010 Device for packing electronic components using injection molding technology
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US Patent 7217595 Sealed three dimensional metal bonded integrated circuits
‌
US Patent 7217614 Methods to form electronic devices and methods to form a material over a semiconductive substrate
‌
US Patent 7217622 Semiconductor device and method of manufacturing the semiconductor device
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US Patent 7217644 Method of manufacturing MOS devices with reduced fringing capacitance
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US Patent 7217647 Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern
‌
US Patent 7217648 Post-ESL porogen burn-out for copper ELK integration
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US Patent 7217655 Electroplated CoWP composite structures as copper barrier layers
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US Patent 7220606 Integrated circuit identification
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US Patent 7220618 Method for forming a redistribution layer in a wafer structure
‌
US Patent 7220623 Method for manufacturing silicide and semiconductor with the silicide
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US Patent 7220644 Single-pole component manufacturing
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US Patent 7220660 Surface planarization of thin silicon films during and after processing by the sequential lateral solidification method
‌
US Patent 7221056 Semiconductor integrated circuit device and manufacturing method thereof
‌
US Patent 7223626 Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers
‌
US Patent 7223636 Manufacturing method of semiconductor device and semiconductor device
‌
US Patent 7223641 Semiconductor device, method for manufacturing the same, liquid crystal television and EL television
‌
US Patent 7223645 Semiconductor device with mushroom electrode and manufacture method thereof
‌
US Patent 7223651 Dram memory cell with a trench capacitor and method for production thereof
‌
US Patent 7223666 Semiconductor device that includes a silicide region that is not in contact with the lightly doped region
‌
US Patent 7223680 Method of forming a dual damascene metal trace with reduced RF impedance resulting from the skin effect
‌
US Patent 7223685 Damascene fabrication with electrochemical layer removal
‌
US Patent 7223691 Method of forming low resistance and reliable via in inter-level dielectric interconnect
‌
US Patent 7223694 Method for improving selectivity of electroless metal deposition
‌
US Patent 7224028 Semiconductor device that includes a gate insulating layer with three different thicknesses
‌
US Patent 7226817 Method of manufacturing
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US Patent 7226821 Flip chip die assembly using thin flexible substrates
‌
US Patent 7226822 Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof
‌
US Patent 7226828 Architecture to monitor isolation integrity between floating gate and source line
‌
US Patent 7226832 Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
‌
US Patent 7226854 Methods of forming metal lines in semiconductor devices
‌
US Patent 7229845 Automated sourcing of substrate microfabrication defects using defects signatures
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US Patent 7229873 Process for manufacturing dual work function metal gates in a microelectronics device
‌
US Patent 7229886 Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein
‌
US Patent 7229889 Methods for metal plating of gate conductors and semiconductors formed thereby
‌
US Patent 7229894 Active cell isolation body of a semiconductor device and method for forming the same
‌
US Patent 7229906 Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
‌
US Patent 7229924 Surface barriers for copper and silver interconnects produced by a damascene process
‌
US Patent 7229933 Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor
‌
US Patent 7232704 Semiconductor device assembly method and semiconductor device assembly apparatus
‌
US Patent 7232720 Method for fabricating a semiconductor device having an insulation film with reduced water content
‌
US Patent 7232729 Method for manufacturing a double bitline implant
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US Patent 7232746 Method for forming dual damascene interconnection in semiconductor device
‌
US Patent 7232747 Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formation
‌
US Patent 7232756 Nickel salicide process with reduced dopant deactivation
‌
US Patent 7232758 Method of correcting lithographic process and method of forming overlay mark
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US Patent 7232773 Liquid drop jetting apparatus using charged beam and method for manufacturing a pattern using the apparatus
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US Patent 7233155 Electrooptic device, electronic apparatus, and method for making the electrooptic device
‌
US Patent 7235420 Process for removing an organic layer during fabrication of an organic electronic device and the organic electronic device formed by the process
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US Patent 7235449 Method of forming a gate oxide film for a high voltage region of a flash memory device
‌
US Patent 7235495 Controlled growth of highly uniform, oxide layers, especially ultrathin layers
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US Patent 7238542 Manufacturing method for compound semiconductor device
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US Patent 7238573 Method for fabricating a trench transistor of semiconductor device
‌
US Patent 7238577 Method of manufacturing self-aligned n and p type stripes for a superjunction device
‌
US Patent 7238578 Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions
‌
US Patent 7238604 Forming thin hard mask over air gap or porous dielectric
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US Patent 7238626 Chemically and electrically stabilized polymer films
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US Patent 7238629 Deposition method, method of manufacturing semiconductor device, and semiconductor device
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US Patent 7241646 Semiconductor device having voltage output function trim circuitry and method for same
‌
US Patent 7241647 Graded semiconductor layer
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US Patent 7241684 Method of forming metal wiring of semiconductor device
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US Patent 7241703 Film forming method for semiconductor device
‌
US Patent 7244635 Semiconductor device and method of manufacturing the same
‌
US Patent 7244642 Method to obtain fully silicided gate electrodes
‌
US Patent 7244647 Embedded capacitor structure in circuit board and method for fabricating the same
‌
US Patent 7247177 Production method for electric double-layer capacitor
‌
US Patent 7247178 Capacitor and method for producing the same, and circuit board with a built-in capacitor and method for producing the same
‌
US Patent 7247508 Semiconductor device with intermediate connector
‌
US Patent 7247540 Methods of forming field effect transistors having recessed channel regions
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US Patent 7247555 Method to control dual damascene trench etch profile and trench depth uniformity
‌
US Patent 7247582 Deposition of tensile and compressive stressed materials
‌
US Patent 7248310 Flat panel energized by blue LED for generating white light
‌
US Patent 7250322 Method of making microsensor
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US Patent 7250329 Method of fabricating a built-in chip type substrate
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US Patent 7250355 Multilayered circuit substrate, semiconductor device and method of producing same
‌
US Patent 7253021 Transfer molding apparatus and method for manufacturing semiconductor devices
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US Patent 7253032 Method of flattening a crystallized semiconductor film surface by using a plate
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US Patent 7253033 Method of manufacturing a semiconductor device that includes implanting in multiple directions a high concentration region
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US Patent 7253082 Pasted SOI substrate, process for producing the same and semiconductor device
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US Patent 7253083 Method of thinning a semiconductor structure
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US Patent 7253092 Tungsten plug corrosion prevention method using water
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US Patent 7256091 Method of manufacturing a semiconductor device with a self-aligned polysilicon electrode
‌
US Patent 7256124 Method of fabricating semiconductor device
‌
US Patent 7256141 Interface layer between dual polycrystalline silicon layers
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US Patent 7256147 Porous body and manufacturing method therefor
‌
US Patent 7256148 Method for treating a wafer edge
‌
US Patent 7259046 Semiconductor device and manufacturing method thereof
‌
US Patent 7259065 Method of forming trench in semiconductor device
‌
US Patent 7259069 Semiconductor device and method of manufacturing the same
‌
US Patent 7259080 Glass-type planar substrate, use thereof, and method for the production thereof
‌
US Patent 7262064 Magnetoresistive effect element, magnetic memory element magnetic memory device and manufacturing methods thereof
‌
US Patent 7262066 Systems and methods for thin film thermal diagnostics with scanning thermal microstructures
‌
US Patent 7262079 Consolidated flip chip BGA assembly process and apparatus
‌
US Patent 7262110 Trench isolation structure and method of formation
‌
US Patent 7262122 Method of forming metal line in semiconductor memory device
‌
US Patent 7264993 Method for producing information carriers
‌
US Patent 7264995 Method for manufacturing wafer level chip scale package using redistribution substrate
‌
US Patent 7264998 Method of removing unnecessary matter from semiconductor wafer, and apparatus using the same
‌
US Patent 7265012 Formation of standard voltage threshold and low voltage threshold MOSFET devices
‌
US Patent 7265023 Fabrication method for a semiconductor structure
‌
US Patent 7265377 Organic semiconductor device
‌
US Patent 7268018 Method for fabricating semiconductor component with stiffener and circuit decal
‌
US Patent 7268025 Pixel structure and fabricating method thereof
‌
US Patent 7268028 Well isolation trenches (WIT) for CMOS devices
‌
US Patent 7268037 Method for fabricating microchips using metal oxide masks
‌
US Patent 7268043 Semiconductor device and method of manufacturing the same
‌
US Patent 7268047 Semiconductor device and method for manufacturing the same
‌
US Patent 7268054 Methods for increasing photo-alignment margins
‌
US Patent 7268056 Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device
‌
US Patent 7268062 Method of crystallizing a semiconductor film using laser irradiation
‌
US Patent 7268065 Methods of manufacturing metal-silicide features
‌
US Patent 7271018 Method of forming a support frame for semiconductor packages
‌
US Patent 7271028 High density electronic interconnection
‌
US Patent 7271047 Test structure and method for measuring the resistance of line-end vias
‌
US Patent 7271051 Methods of forming a plurality of capacitor devices
‌
US Patent 7271052 Long retention time single transistor vertical memory gain cell
‌
US Patent 7271075 Method and a device for bonding two plate-shaped objects
‌
US Patent 7271083 One-transistor random access memory technology compatible with metal gate process
‌
US Patent 7271098 Method of fabricating a desired pattern of electronically functional material
‌
US Patent 7273761 Box-in-box field-to-field alignment structure
‌
US Patent 7273774 Method for making thin-film semiconductor device
‌
US Patent 7273778 Method of electroplating a substance over a semiconductor substrate
‌
US Patent 7273814 Method for forming a ruthenium metal layer on a patterned substrate
‌
US Patent 7274048 Substrate based ESD network protection for a flip chip
‌
US Patent 7276091 Method of producing polymer capacitor by forming micropore in ion exchange membrane and polymer capacitor produced thereby
‌
US Patent 7276388 Method, system, and apparatus for authenticating devices during assembly
‌
US Patent 7276396 Die handling system
‌
US Patent 7276431 Method of fabricating isolated semiconductor devices in epi-less substrate
‌
US Patent 7276435 Die level metal density gradient for improved flip chip package reliability
‌
US Patent 7276437 Semiconductor device and manufacturing method thereof
‌
US Patent 7276457 Selective heating using flash anneal
‌
US Patent 7279369 Germanium on insulator fabrication via epitaxial germanium bonding
‌
US Patent 7279380 Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method
‌
US Patent 7279393 Trench isolation structure and method of manufacture therefor
‌
US Patent 7279396 Methods of forming trench isolation regions with nitride liner
‌
US Patent 7279408 Semiconductor device, method for manufacturing the same, and plating solution
‌
US Patent 7279433 Deposition and patterning of boron nitride nanotube ILD
‌
US Patent 7282376 System, method, and apparatus for electrically testing lead-to-lead shorting during magnetoresistive sensor fabrication
‌
US Patent 7282385 Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus
‌
US Patent 7282413 Semiconductor device including nonvolatile memory and method for fabricating the same
‌
US Patent 7282447 Method for an integrated circuit contact
‌
US Patent 7285431 Method for manufacturing a GaN based LED of a black hole structure
‌
US Patent 7285451 Semiconductor integrated circuit device manufacturing method
‌
US Patent 7285473 Method for fabricating low-defect-density changed orientation Si
‌
US Patent 7285486 Ball transferring method and apparatus
‌
US Patent 7285487 Method and apparatus for network with multilayer metalization
‌
US Patent 7285855 Packaged device and method of forming same
‌
US Patent 7288433 Method of making assemblies having stacked semiconductor chips
‌
US Patent 7288465 Semiconductor wafer front side protection
‌
US Patent 7288475 Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner
‌
US Patent 7288482 Silicon nitride etching methods
‌
US Patent 7288839 Apparatus and methods for cooling semiconductor integrated circuit package structures
‌
US Patent 7291507 Using a time invariant statistical process variable of a semiconductor chip as the chip identifier
‌
US Patent 7291510 Method for manufacturing semiconductor device
‌
US Patent 7291516 Low temperature melt-processing of organic-inorganic hybrid
‌
US Patent 7291527 Work function control of metals
‌
US Patent 7291533 Method for production of trench DRAM cells and a trench DRAM cell array with fin field-effect transistors with a curved channel (CFET—curved fets)
‌
US Patent 7291542 Semiconductor wafer and manufacturing method thereof
‌
US Patent 7291558 Copper interconnect wiring and method of forming thereof
‌
US Patent 7294522 CMOS image sensor and method for fabricating the same
‌
US Patent 7294531 Wafer level chip stack method
‌
US Patent 7294536 Process for manufacturing an SOI wafer by annealing and oxidation of buried channels
‌
US Patent 7294547 SONOS memory cell having a graded high-K dielectric
‌
US Patent 7294553 Plasma-enhanced chemical vapour deposition process for depositing silicon nitride or silicon oxynitride, process for producing one such layer arrangement, and layer arrangement
‌
US Patent 7294560 Method of assembling one-dimensional nanostructures
‌
US Patent 7294570 Contact integration method
‌
US Patent 7294582 Low temperature silicon compound deposition
‌
US Patent 7297557 Method for chemically bonding Langmuir-Blodgett films to substrates
‌
US Patent 7297561 Pattern for improved visual inspection of semiconductor devices
‌
US Patent 7297578 Method for producing a field effect transistor
‌
US Patent 7297581 SRAM formation using shadow implantation
‌
US Patent 7297584 Methods of fabricating semiconductor devices having a dual stress liner
‌
US Patent 7297607 Device and method of performing a seasoning process for a semiconductor device manufacturing apparatus
‌
US Patent 7297624 Semiconductor device and method for fabricating the same
‌
US Patent 7297630 Methods of fabricating via hole and trench
‌
US Patent 7297640 Method for reducing argon diffusion from high density plasma films
‌
US Patent 7297641 Method to form ultra high quality silicon-containing compound layers
‌
US Patent 7300832 Semiconductor manufacturing method using two-stage annealing
‌
US Patent 7300862 Method for manufacturing semiconductor device
‌
US Patent 7300868 Damascene interconnection having porous low k layer with a hard mask reduced in thickness
‌
US Patent 7300873 Systems and methods for forming metal-containing layers using vapor deposition processes
‌
US Patent 7300875 Post metal chemical mechanical polishing dry cleaning
‌
US Patent 7302468 Local area preference determination system and method
‌
US Patent 7303928 Process monitor and system for producing semiconductor
‌
US Patent 7303947 Source bridge for cooling and/or external connection
‌
US Patent 7303950 Semiconductor device, method of manufacturing same and method of designing same
‌
US Patent 7303956 Flash memory cell arrays having dual control gates per memory cell charge storage element
‌
US Patent 7303968 Semiconductor device and method having multiple subcollectors formed on a common wafer
‌
US Patent 7303977 Laser micromachining method
‌
US Patent 7303984 Semiconductor substrate structure and processing method thereof
‌
US Patent 7303988 Methods of manufacturing multi-level metal lines in semiconductor devices
‌
US Patent 7304002 Method of oxidizing member to be treated
‌
US Patent 7304003 Oxidizing method and oxidizing unit for object to be processed
‌
US Patent 7304332 Compound semiconductor epitaxial substrate and method for manufacturing same
‌
US Patent 7306957 Fabrication method of semiconductor integrated circuit device
‌
US Patent 7306959 Methods of fabricating integrated optoelectronic devices
‌
US Patent 7306971 Semiconductor chip packaging method with individually placed film adhesive pieces
‌
US Patent 7306974 Microelectronic devices and methods for manufacturing and operating packaged microelectronic device assemblies
‌
US Patent 7306979 Method of fabricating thin film transistor substrate for display device
‌
US Patent 7306998 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect
‌
US Patent 7307001 Wafer repair method using direct-writing
‌
US Patent 7307018 Method of fabricating conductive lines
‌
US Patent 7307316 Thin film transistor
‌
US Patent 7309627 Method for fabricating a gate mask of a semiconductor device
‌
US Patent 7309635 Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels
‌
US Patent 7309645 Semiconductor thin film crystallization method
‌
US Patent 7312092 Methods for fabrication of localized membranes on single crystal substrate surfaces
‌
US Patent 7312125 Fully depleted strained semiconductor on insulator transistor and method of making the same
‌
US Patent 7312127 Incorporating dopants to enhance the dielectric properties of metal silicates
‌
US Patent 7312129 Method for producing two gates controlling the same channel
‌
US Patent 7312135 Laser processing apparatus
‌
US Patent 7312142 Method for making cable with a conductive bump array, and method for connecting the cable to a task object
‌
US Patent 7312163 Atomic layer deposition methods, and methods of forming materials over semiconductor substrates
‌
US Patent 7312164 Selective passivation of exposed silicon
‌
US Patent 7312165 Codeposition of hafnium-germanium oxides on substrates used in or for semiconductor devices
‌
US Patent 7314786 Metal resistor, resistor material and method
‌
US Patent 7314789 Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification
‌
US Patent 7314792 Method for fabricating transistor of semiconductor device
‌
US Patent 7314795 Methods of forming electronic devices including electrodes with insulating spacers thereon
‌
US Patent 7314801 Semiconductor device having a surface conducting channel and method of forming
‌
US Patent 7314803 Method for producing a semiconductor structure
‌
US Patent 7314808 Method for sequencing substrates
‌
US Patent 7315078 Chip-stacked semiconductor package and method for fabricating the same
‌
US Patent 7316944 Fabricating method of a liquid crystal display device
‌
US Patent 7316947 Method of manufacturing a semiconductor device
‌
US Patent 7316951 Fabrication method for a trench capacitor having an insulation collar
‌
US Patent 7316967 Flow method and reactor for manufacturing noncrystals
‌
US Patent 7316972 Contact hole formation method
‌
US Patent 7316982 Controlling carbon nanotubes using optical traps
‌
US Patent 7319051 Thermally enhanced metal capped BGA package
‌
US Patent 7319052 Alloying method, and wiring forming method, display device forming method, and image display unit fabricating method
‌
US Patent 7319060 Semiconductor device and method of manufacturing the semiconductor device
‌
US Patent 7320916 Manufacturing method of semiconductor device
‌
US Patent 7320935 Semiconductor device using an interconnect
‌
US Patent 7320939 Semiconductor device fabricated by a method of reducing the contact resistance of the connection regions
‌
US Patent 7323017 Nitrided valve metal material and method of making same
‌
US Patent 7323360 Electronic assemblies with filled no-flow underfill
‌
US Patent 7323364 Stacked module systems and method
‌
US Patent 7323373 Method of forming a semiconductor device with decreased undercutting of semiconductor material
‌
US Patent 7323392 High performance transistor with a highly stressed channel
‌
US Patent 7323403 Multi-step process for patterning a metal gate electrode
‌
US Patent 7323406 Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures
‌
US Patent 7323426 High strain point glasses
‌
US Patent 7326261 Surface-mount capacitor and method of producing the same
‌
US Patent 7326589 Method for producing a TFA image sensor and one such TFA image sensor
‌
US Patent 7326594 Connecting a plurality of bond pads and/or inner leads with a single bond wire
‌
US Patent 7326608 Fin field effect transistor and method of manufacturing the same
‌
US Patent 7326614 Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
‌
US Patent 7326627 Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device
‌
US Patent 7326635 Method and apparatus for stripping photo-resist
‌
US Patent 7326646 Nitrogen-free ARC layer and a method of manufacturing the same
‌
US Patent 7329548 Integration processes for fabricating a conductive metal oxide gate ferroelectric memory transistor
‌
US Patent 7329549 Monitoring method of processing state and processing unit
‌
US Patent 7329553 Method of fabricating one-way transparent optical system
‌
US Patent 7329561 Fabricating memory components (PCRAMS) including memory cells based on a layer that changes phase state
‌
US Patent 7329563 Method for fabrication of wafer level package incorporating dual compliant layers
‌
US Patent 7329570 Method for manufacturing a semiconductor device
‌
US Patent 7329571 Technique for providing multiple stress sources in NMOS and PMOS transistors
‌
US Patent 7329572 Method of forming PIP capacitor
‌
US Patent 7329583 Method of fabricating isolated semiconductor devices in epi-less substrate
‌
US Patent 7329594 Method of manufacturing a semiconductor device
‌
US Patent 7329617 Coating for enhancing adhesion of molding compound to semiconductor devices
‌
US Patent 7329942 Array-type modularized light-emitting diode structure and a method for packaging the structure
‌
US Patent 7331999 Method of producing solid electrolytic capacitor
‌
US Patent 7332360 Early detection of metal wiring reliability using a noise spectrum
‌
US Patent 7332361 Xerographic micro-assembler
‌
US Patent 7332374 Prealignment and gapping for RF substrates
‌
US Patent 7332377 Manufacturing method with self-aligned arrangement of solid body electrolyte memory cells of minimum structure size
‌
US Patent 7332378 Integrated circuit memory system with dummy active region
‌
US Patent 7332385 Method of manufacturing a semiconductor device that includes gettering regions
‌
US Patent 7332390 Semiconductor memory device and fabrication thereof
‌
US Patent 7332391 Method for forming storage node contacts in semiconductor device
‌
US Patent 7332396 Semiconductor device with recessed trench and method of fabricating the same
‌
US Patent 7332405 Method of forming alignment marks for semiconductor device fabrication
‌
US Patent 7332414 Chemical die singulation technique
‌
US Patent 7332422 Method for CuO reduction by using two step nitrogen oxygen and reducing plasma treatment
‌
US Patent 7335530 Freeform substrates and devices
‌
US Patent 7335539 Method for making thin-film semiconductor device
‌
US Patent 7335554 Method for fabricating semiconductor
‌
US Patent 7335555 Buried-contact solar cells with self-doping contacts
‌
US Patent 7335558 Method of manufacturing NAND flash memory device
‌
US Patent 7335561 Semiconductor integrated circuit device and manufacturing method thereof
‌
US Patent 7335564 Method for forming device isolation layer of semiconductor device
‌
US Patent 7335565 Metal-oxide-semiconductor device having improved performance and reliability
‌
US Patent 7335571 Method of making a semiconductor device having an opening in a solder mask
‌
US Patent 7335575 Semiconductor constructions and semiconductor device fabrication methods
‌
US Patent 7335581 Semiconductor memory device and method of manufacturing the same
‌
US Patent 7335596 Method for fabricating copper-based interconnections for semiconductor device
‌
US Patent 7335609 Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials
‌
US Patent 7338815 Semiconductor device manufacturing method
‌
US Patent 7338826 Silicon nitride passivation with ammonia plasma pretreatment for improving reliability of AlGaN/GaN HEMTs
‌
US Patent 7338838 Resin-encapsulation semiconductor device and method for fabricating the same
‌
US Patent 7338845 Fabrication method of a low-temperature polysilicon thin film transistor
‌
US Patent 7338853 High power radio frequency integrated circuit capable of impeding parasitic current loss
‌
US Patent 7338884 Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device
‌
US Patent 7338886 Implantation-less approach to fabricating strained semiconductor on isolation wafers
‌
US Patent 7338889 Method of improving copper interconnects of semiconductor devices for bonding
‌
US Patent 7341608 Method for making a device of storing energy, enhancing the efficiency of manufacture and the reliability of products
‌
US Patent 7341875 Semiconductor memory device with a capacitor formed therein and a method for forming the same
‌
US Patent 7341877 Calibration method in a chip mounting device
‌
US Patent 7341893 Structure and method for thin film device
‌
US Patent 7341899 Method of fabricating a thin film transistor
‌
US Patent 7341902 Finfet/trigate stress-memorization method
‌
US Patent 7341907 Single wafer thermal CVD processes for hemispherical grained silicon and nano-crystalline grain-sized polysilicon
‌
US Patent 7341914 Method for forming a non-volatile memory and a peripheral device on a semiconductor substrate
‌
US Patent 7341922 Dry etching method, fabrication method for semiconductor device, and dry etching apparatus
‌
US Patent 7344048 Dispensing device and analyzing apparatus
‌
US Patent 7344898 Method for manufacturing semiconductor device
‌
US Patent 7344908 Atomic force microscope cantilever including field effect transistor and method for manufacturing the same
‌
US Patent 7344926 Liquid crystal display device and method of manufacturing the same
‌
US Patent 7344929 Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity
‌
US Patent 7344934 CMOS transistor and method of manufacture thereof
‌
US Patent 7344938 Method of fabricating memory
‌
US Patent 7344951 Surface preparation method for selective and non-selective epitaxial growth
‌
US Patent 7344955 Cut-and-paste imprint lithographic mold and method therefor
‌
US Patent 7344957 SOI wafer with cooling channels and a method of manufacture thereof
‌
US Patent 7344958 Method for wafer bonding (A1, In, Ga)N and Zn(S, Se) for optoelectronic applications
‌
US Patent 7344965 Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gaseous additions
‌
US Patent 7344972 Photosensitive dielectric layer
‌
US Patent 7344976 Method for fabricating nonvolatile semiconductor memory device
‌
US Patent 7344983 Clustered surface preparation for silicide and metal contacts
‌
US Patent 7344984 Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors
‌
US Patent 7344993 Low-pressure removal of photoresist and etch residue
‌
US Patent 7345000 Method and system for treating a dielectric film
‌
US Patent 7345003 Semiconductor device manufacturing method, wafer, and wafer manufacturing method
‌
US Patent 7347228 Method of making semiconductor devices
‌
US Patent 7348192 Method for monitoring film thickness, a system for monitoring film thickness, a method for manufacturing a semiconductor device, and a program product for controlling film thickness monitoring system
‌
US Patent 7348202 CMOS image sensor and method for fabricating the same
‌
US Patent 7348216 Rework process for removing residual UV adhesive from C4 wafer surfaces
‌
US Patent 7348222 Method for manufacturing a thin film transistor and method for manufacturing a semiconductor device
‌
US Patent 7348248 CMOS transistor with high drive current and low sheet resistance
‌
US Patent 7348249 Method for manufacturing semiconductor device
‌
US Patent 7348254 Method of fabricating fin field-effect transistors
‌
US Patent 7348258 Method and device for controlled cleaving process
‌
US Patent 7348263 Manufacturing method for electronic component, electronic component, and electronic equipment
‌
US Patent 7348272 Method of fabricating interconnect
‌
US Patent 7348280 Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions
‌
US Patent 7348283 Mechanically robust dielectric film and stack
‌
US Patent 7351597 Fabrication method of semiconductor integrated circuit device
‌
US Patent 7351603 Process of making a microtube and microfluidic devices formed therewith
‌
US Patent 7351609 Method for wafer level package of sensor chip
‌
US Patent 7351627 Method of manufacturing semiconductor device using gate-through ion implantation
‌
US Patent 7351632 Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon
‌
US Patent 7351633 Method of fabricating semiconductor device using selective epitaxial growth
‌
US Patent 7351635 Method of fabricating microelectronic device using super critical fluid
‌
US Patent 7351638 Scanning laser thermal annealing
‌
US Patent 7351643 Method of manufacturing a semiconductor device
‌
US Patent 7351666 Layout and process to contact sub-lithographic structures
‌
US Patent 7351668 Film formation method and apparatus for semiconductor process
‌
US Patent 7351670 Method for producing silicon nitride films and process for fabricating semiconductor devices using said method
‌
US Patent 7354781 Method of manufacturing field emission device
‌
US Patent 7354790 Method and apparatus for avoiding dicing chip-outs in integrated circuit die
‌
US Patent 7354794 Printed conductive connectors
‌
US Patent 7354808 Resist composition and method for manufacturing semiconductor device using the same
‌
US Patent 7354822 Method of forming a MOSFET with dual work function materials
‌
US Patent 7354824 Fabrication method of non-volatile memory
‌
US Patent 7354835 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby
‌
US Patent 7354836 Technique for forming a strained transistor by a late amorphization and disposable spacers
‌
US Patent 7354841 Method for fabricating photodiode of CMOS image sensor
‌
US Patent 7354845 In-line process for making thin film electronic devices
‌
US Patent 7354855 Semiconductor device and a method of manufacturing the same
‌
US Patent 7354862 Thin passivation layer on 3D devices
‌
US Patent 7355266 Semiconductor wafer test system
‌
US Patent 7358113 Processing systems and methods for molecular memory
‌
US Patent 7358116 Substrate conductive post formation
‌
US Patent 7358143 Semiconductor device
‌
US Patent 7358146 Method of forming a capacitor
‌
US Patent 7358147 Process for producing SOI wafer
‌
US Patent 7358152 Wafer bonding of thinned electronic materials and circuits to high performance substrate
‌
US Patent 7358158 Wafer machining adhesive tape, and its manufacturing method and using method
‌
US Patent 7358162 Method of manufacturing semiconductor device
‌
US Patent 7358170 Methods of forming conductive interconnects, and methods of depositing nickel
‌
US Patent 7358172 Poly filled substrate contact on SOI structure
‌
US Patent 7358175 Serial thermal processor arrangement
‌
US Patent 7358201 Methods of forming channels on an integrated circuit die and die cooling systems including such channels
‌
US Patent 7361523 Three-axis accelerometer
‌
US Patent 7361537 Method of fabricating recess channel array transistor
‌
US Patent 7361541 Programming optical device
‌
US Patent 7361551 Method for making an integrated circuit having an embedded non-volatile memory
‌
US Patent 7361553 Semiconductor device manufacturing method
‌
US Patent 7361555 Trench-gate transistors and their manufacture
‌
US Patent 7361564 Method of manufacturing high-voltage device
‌
US Patent 7361569 Methods for increasing photo-alignment margins
‌
US Patent 7361597 Semiconductor device and method of fabricating the same
‌
US Patent 7361612 Barrier coating compositions containing silicon and methods of forming photoresist patterns using the same
‌
US Patent 11181006 Turbine tip shroud assembly with plural shroud segments having inter-segment seal arrangement
‌
US Patent 11181011 Lighter-weight casing made of composite material and method of manufacturing same
‌
US Patent 11181118 Method for controlling fans and a group of fans
‌
US Patent 11181125 Fan frame body with damping structure and fan thereof
‌
US Patent 11181324 Cooling system for heat generating components in a fairing
‌
US Patent 11183509 Non-volatile memory with silicided bit line contacts
‌
US Patent 7364925 Organic light emitting device having a protective barrier
‌
US Patent 7364938 Method for production of a semiconductor device with auto-aligned metallisations
‌
US Patent 7364948 Method for fabricating semiconductor package
‌
US Patent 7364951 Nonvolatile semiconductor memory device and method for manufacturing the same
‌
US Patent 7364957 Method and apparatus for semiconductor device with improved source/drain junctions
‌
US Patent 7364971 Method for manufacturing semiconductor device having super junction construction
‌
US Patent 7364975 Semiconductor device fabrication methods
‌
US Patent 7364987 Method for manufacturing semiconductor device
‌
US Patent 7364991 Buffer-layer treatment of MOCVD-grown nitride structures
‌
US Patent 7365000 Method for fabricating semiconductor device
‌
US Patent 7365002 Method of manufacturing a semiconductor device
‌
US Patent 7365021 Methods of fabricating a semiconductor device using an organic compound and fluoride-based buffered solution
‌
US Patent 7365022 Additive printed mask process and structures produced thereby
‌
US Patent 7365805 Display device, manufacturing method thereof, and television receiver
‌
US Patent 7368309 Nitride semiconductor and fabrication method thereof
‌
US Patent 7368322 Method for mounting a chip on a base and arrangement produced by this method
‌
US Patent 7368324 Method of manufacturing self-supporting contacting structures
‌
US Patent 7368334 Silicon-on-insulator chip with multiple crystal orientations
‌
US Patent 7368336 Organic insulator, organic thin film transistor array panel including organic insulator, and manufacturing method therefor
‌
US Patent 7368352 Semiconductor devices having transistors with vertical channels and method of fabricating the same
‌
US Patent 7368356 Transistor with doped gate dielectric
‌
US Patent 7368362 Methods for increasing photo alignment margins
‌
US Patent 7368370 Site-specific nanoparticle self-assembly
‌
US Patent 7368371 Silicon carbide Schottky diode and method of making the same
‌
US Patent 7368373 Method for manufacturing semiconductor devices and plug
‌
US Patent 7368384 Film formation apparatus and method of using the same
‌
US Patent 7368391 Methods for designing carrier substrates with raised terminals
‌
US Patent 7371637 Oxide-nitride stack gate dielectric
‌
US Patent 7371648 Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same
‌
US Patent 7371655 Method of fabricating low-power CMOS device
‌
US Patent 7371668 Method for making a metal oxide semiconductor device
‌
US Patent 7371671 System and method for photolithography in semiconductor manufacturing
‌
US Patent 7371673 Method and apparatus for attaching an IC package to a PCB assembly
‌
US Patent 7371680 Method of manufacturing semiconductor device
‌
US Patent 7371683 Method for carrying object to be processed
‌
US Patent 7371688 Removal of transition metal ternary and/or quaternary barrier materials from a substrate
‌
US Patent 7374585 Method for producing solid electrolytic capacitor
‌
US Patent 7374975 Method of fabricating a transistor
‌
US Patent 7374977 Droplet discharge device, and method for forming pattern, and method for manufacturing display device
‌
US Patent 7374992 Manufacturing method for an integrated semiconductor structure
‌
US Patent 7374996 Structured, electrically-formed floating gate for flash memories
‌
US Patent 7374999 Semiconductor device
‌
US Patent 7375004 Method of making an isolation trench and resulting isolation trench
‌
US Patent 7378287 Wafer matching methods for use in assembling micromirror array devices
‌
US Patent 7378293 MEMS fabrication method
‌
US Patent 7378319 Method of forming double gate dielectric layers and semiconductor device having the same
‌
US Patent 7378323 Silicide process utilizing pre-amorphization implant and second spacer
‌
US Patent 7378339 Barrier for use in 3-D integration of circuits
‌
US Patent 7378358 Method for forming insulating film on substrate, method for manufacturing semiconductor device and substrate-processing apparatus
‌
US Patent 7384806 Method for characterizing defects on semiconductor wafers
‌
US Patent 7390701 Method of forming a digitalized semiconductor structure
‌
US Patent 7390756 Atomic layer deposited zirconium silicon oxide films
‌
US Patent 7391104 Non-stick detection method and mechanism for array molded laminate packages
‌
US Patent 7393737 Semiconductor device and a method of manufacturing the same
‌
US Patent 7399669 Semiconductor devices and methods for fabricating the same including forming an amorphous region in an interface between a device isolation layer and a source/drain diffusion layer
‌
US Patent 7405116 Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow
‌
US Patent 7413939 Method of growing a germanium epitaxial film on insulator for use in fabrication of CMOS integrated circuit
‌
US Patent 7435664 Wafer-level bonding for mechanically reinforced ultra-thin die
‌
US Patent 7442589 System and method for uniform multi-plane silicon oxide layer formation for optical applications
‌
US Patent 7446020 Wafer dividing method and dividing apparatus
‌
US Patent 11187103 System configuration and operation method for improving steam turbine power generation efficiency
‌
US Patent 11187202 Power generating apparatus
‌
US Patent 11187241 Portable blowing device
‌
US Patent 7988416 Wind turbine blade with damping element
‌
US Patent 7989250 Membrane grating for beam steering device and method of fabricating same
‌
US Patent 7994559 Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same
‌
US Patent 8007236 Supporting system for suspended wind turbines
‌
US Patent 8007238 Hanging fan with a ceiling mount structure
‌
US Patent 8007242 High temperature turbine rotor blade
‌
US Patent 8008124 Adhesive film for semiconductor and semiconductor device using the adhesive film
‌
US Patent 8008704 Nonvolatile semiconductor memory device and method of manufacturing the same
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US Patent 8007238 Hanging fan with a ceiling mount structure
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Patent primary examiner of
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US Patent 7446020 Wafer dividing method and dividing apparatus
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Golden AI
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Golden AI
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Patent primary examiner of
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US Patent 7435664 Wafer-level bonding for mechanically reinforced ultra-thin die
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Golden AI
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Golden AI
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