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Dung A. Le

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godwinno feliks
edited on 26 Jul, 2022
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Golden AI
edited on 15 Dec, 2021
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Patent primary examiner of
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US Patent 7087984 Methods for protecting intermediate conductive elements of semiconductor device assemblies
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US Patent 7091057 Method of making a single-crystal-silicon 3D micromirror
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US Patent 7091092 Process flow for a performance enhanced MOSFET with self-aligned, recessed channel
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US Patent 7091136 Method of forming semiconductor compound film for fabrication of electronic device and film produced by same
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US Patent 7091138 Forming method and a forming apparatus of nanocrystalline silicon structure
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US Patent 7094620 Semiconductor device manufacturing method
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US Patent 7094642 Method of fabricating semiconductor device
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US Patent 7094655 Method of fabricating semiconductor device
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US Patent 7094691 MOCVD of tungsten nitride thin films using W(CO)
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US Patent 7095088 System and device including a barrier layer
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US Patent 7098151 Method of manufacturing carbon nanotube semiconductor device
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US Patent 7105424 Method for preparing arylphosphonite antioxidant
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US Patent 7105459 Method for forming thin film
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US Patent 7109525 Point source light-emitting diode
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US Patent 7109530 Nitride-based semiconductor element
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US Patent 7109537 CMOS pixel with dual gate PMOS
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US Patent 7112501 Method of fabrication a silicon-on-insulator device with a channel stop
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US Patent 7115465 Method for manufacturing a bipolar transistor
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US Patent 7115472 Process for manufacturing a dual charge storage location memory cell
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US Patent 7118925 Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step
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US Patent 7118971 Method for fabricating trench power device
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US Patent 7118983 Method of fabricating semiconductor device
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US Patent 7119028 Surface imprinted films with carbon nanotubes
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US Patent 7119388 MRAM device fabricated using chemical mechanical polishing
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US Patent 7122425 Methods of forming semiconductor constructions
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US Patent 7125738 Method of fabricating a photosensitive structure
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US Patent 7126193 Metal-oxide-semiconductor device with enhanced source electrode
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US Patent 7126195 Method for forming a metallization layer
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US Patent 7129167 Methods and systems for a stress-free cleaning a surface of a substrate
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US Patent 7132359 Tolerance bondwire inductors for analog circuitry
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US Patent 7132709 Semiconductor device including a capacitor having a capacitive insulating film of an insulating metal oxide
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US Patent 7132733 Semiconductor device
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US Patent 11177207 Compact transistor utilizing shield structure arrangement
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US Patent 11177439 Processing of perovskite films using inks with complexing agents
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US Patent 7141474 Fabrication method of a nonvolatile semiconductor memory
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US Patent 7141495 Methods and forming structures, structures and apparatuses for forming structures
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US Patent 7144747 Method for thermally treating a substrate that comprises several layers
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US Patent 7145208 MOS transistor having a work-function-dominating layer
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US Patent 7145251 Colored conductive wires for a semiconductor package
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US Patent 7151025 Method of manufacturing a semiconductor device with self-aligned contacts
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US Patent 7153713 Method for manufacturing high efficiency light-emitting diodes
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US Patent 7153770 Method of manufacturing semiconductor device and semiconductor device manufactured using the same
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US Patent 7154183 Semiconductor device having multilevel interconnection
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US Patent 7157332 Method for manufacturing flash memory cell
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US Patent 7157385 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
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US Patent 7160764 Laser annealing method and semiconductor device fabricating method
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US Patent 7160788 Methods of forming integrated circuits
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US Patent 7161206 Non-volatile memory devices
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US Patent 7163829 Method of integration testing for packaged electronic components
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US Patent 7163832 Method for manufacturing CMOS image sensor
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US Patent 7166487 Manufacturing method of optical devices
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US Patent 7169624 Shared bit line cross-point memory array manufacturing method
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US Patent 7169681 Method of forming dual gate dielectric layer
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US Patent 7176118 Circuit constructions
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US Patent 7176119 Method of fabricating copper damascene and dual damascene interconnect wiring
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US Patent 7176133 Controlled electroless plating
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US Patent 7183136 Semiconductor element and method for producing the same
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US Patent 7183153 Method of manufacturing self aligned non-volatile memory cells
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US Patent 7183206 Fabrication of semiconductor devices
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US Patent 7186580 Light emitting diodes (LEDs) with improved light extraction by roughening
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US Patent 7186622 Formation of active area using semiconductor growth process without STI integration
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US Patent 7189656 Method for manufacturing ag-oxide-based electric contact material and product of the same
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US Patent 7189663 Organic semiconductor device having an active dielectric layer comprising silsesquioxanes
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US Patent 7195985 CMOS transistor junction regions formed by a CVD etching and deposition sequence
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US Patent 7199018 Plasma assisted pre-planarization process
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US Patent 7199047 Bi-layer etch stop process for defect reduction and via stress migration improvement
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US Patent 7199466 Package design using thermal linkage from die to printed circuit board
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US Patent 7202544 Giant magnetoresistance structure
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US Patent 7205173 Method of fabricating micro-electromechanical systems
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US Patent 7205202 Semiconductor device and method for regional stress control
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US Patent 7205209 Fabrication of stacked dielectric layer for suppressing electrostatic charge buildup
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US Patent 7205595 Polymer memory device with electron traps
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US Patent 7208414 Method for enhanced uni-directional diffusion of metal and subsequent silicide formation
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US Patent 7211446 Method of patterning a magnetic tunnel junction stack for a magneto-resistive random access memory
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US Patent 7211514 Heat-processing method for semiconductor process under a vacuum pressure
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US Patent 7211819 Damascene phase change memory
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US Patent 7211856 Resistive memory for low-voltage applications
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US Patent 7214565 Manufacturing method of an electronic part built-in substrate
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US Patent 7214583 Memory cell with an asymmetric crystalline structure
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US Patent 7214626 Etching process for decreasing mask defect
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US Patent 7217588 Integrated MEMS packaging
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US Patent 7220601 Method of forming nano-sized MTJ cell without contact hole
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US Patent 7220610 Manufacturing method of array substrate for liquid crystal display device
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US Patent 7220633 Method of fabricating a lateral double-diffused MOSFET
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US Patent 7220639 Method for fabricating a MIM capacitor high-K dielectric for increased capacitance density and related structure
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US Patent 7220659 Method for manufacturing a semiconductor device
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US Patent 7221033 Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
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US Patent 7223682 Method of making a semiconductor device using bump material including a liquid
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US Patent 7223703 Method of forming patterns
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US Patent 7223704 Repair of carbon depletion in low-k dielectric films
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US Patent 7226811 Process for fabricating a leadless plastic chip carrier
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US Patent 7226857 Front-end processing of nickel plated bond pads
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US Patent 7227266 Interconnect structure to reduce stress induced voiding effect
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US Patent 7229909 Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes
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US Patent 7229922 Method for making a semiconductor device having increased conductive material reliability
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US Patent 7232750 Methods involving spin-on polymers that reversibly bind charge carriers
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US Patent 7232761 Method of chemical mechanical polishing with high throughput and low dishing
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US Patent 7235440 Formation of ultra-thin oxide layers by self-limiting interfacial oxidation
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US Patent 7235473 Dual silicide semiconductor fabrication process
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US Patent 7235499 Semiconductor processing methods
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US Patent 7235501 Lanthanum hafnium oxide dielectrics
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US Patent 7238561 Method for forming uniaxially strained devices
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US Patent 7238607 Method to minimize formation of recess at surface planarized by chemical mechanical planarization
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US Patent 7238993 CMOS pixel with dual gate PMOS
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US Patent 7241682 Method of forming a dual damascene structure
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US Patent 7241701 Method and furnace for the vapor phase deposition of components onto semiconductor substrates with a variable main flow direction of the process gas
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US Patent 7242052 Non-volatile memory
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US Patent 7242071 Semiconductor structure
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US Patent 7242100 Method for manufacturing semiconductor device with plural semiconductor chips
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US Patent 7244631 MEMS surface modification for passive control of charge accumulation
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US Patent 7245010 System and device including a barrier layer
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US Patent 7247530 Ultrathin SOI transistor and method of making the same
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US Patent 7247554 Method of making integrated circuits using ruthenium and its oxides as a Cu diffusion barrier
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US Patent 7250340 Method of fabricating programmable structure including discontinuous storage elements and spacer control gates in a trench
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US Patent 7250378 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
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US Patent 7250380 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
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US Patent 7253067 Method for manufacturing a semiconductor device including a shallow trench isolation structure
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US Patent 7253466 Crossbar array microelectronic electrochemical cells
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US Patent 7253488 Piezo-TFT cantilever MEMS
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US Patent 7256142 Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
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US Patent 7256437 Semiconductor storage device which includes a hydrogen diffusion inhibiting layer
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US Patent 7259034 Self-alignment manufacturing method of the microlens and the aperture using in optical devices
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US Patent 7259082 Method of manufacturing semiconductor device
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US Patent 7259393 Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses
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US Patent 7259453 Hexagonal array structure for ball grid array packages
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US Patent 7265049 Ultrathin chemically grown oxide film as a dopant diffusion barrier in semiconductor devices
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US Patent 7265418 Semiconductor devices having field effect transistors
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US Patent 7268088 Formation of low leakage thermally assisted radical nitrided dielectrics
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US Patent 7268397 Thermal dissipation structures for finfets
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US Patent 7271011 Methods of implementing magnetic tunnel junction current sensors
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US Patent 7271024 Method for fabricating sensor semiconductor device
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US Patent 7271053 Methods of forming capacitors and electronic devices
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US Patent 7271062 Non-volatile memory cell and fabricating method thereof and method of fabricating non-volatile memory
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US Patent 7271438 Self-aligned silicide for word lines and contacts
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US Patent 7271447 Semiconductor device
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US Patent 7271485 Systems and methods for distributing I/O in a semiconductor device
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US Patent 7274104 Semiconductor device having an interconnect that increases in impurity concentration as width increases
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US Patent 7276384 Magnetic tunnel junctions with improved tunneling magneto-resistance
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US Patent 7276393 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
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US Patent 7276442 Method for forming a metallization layer
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US Patent 7276732 Thin film transistor array panel
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US Patent 7276752 Methods of forming integrated circuits, and DRAM circuitry memory cells
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US Patent 7276755 Integrated circuit and method of manufacture
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US Patent 7279342 Ferroelectric memory
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US Patent 7279344 Method of forming a nitride-based semiconductor
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US Patent 7279738 Semiconductor device with an analog capacitor
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US Patent 7285456 Method of fabricating a fin field effect transistor having a plurality of protruding channels
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US Patent 7285464 Nonvolatile memory cell comprising a reduced height vertical diode
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US Patent 7285482 Method for producing solid-state imaging device
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US Patent 7285493 Methods of forming a metal layer using transition metal precursors
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US Patent 7285804 Thyristor-based SRAM
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US Patent 7285811 MRAM device for preventing electrical shorts during fabrication
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US Patent 7285840 Apparatus for confining inductively coupled surface currents
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US Patent 7294516 Test patterns and methods of controlling CMP process using the same
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US Patent 7294532 Method for manufacturing semiconductor device
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US Patent 7294572 Method of forming contact
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US Patent 7297583 Method of making strained channel CMOS transistors having lattice-mismatched epitaxial
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US Patent 7300851 Method of fabricating a silicon-on-insulator device with a channel stop
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US Patent 7301236 Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via
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US Patent 7301237 Semiconductor device
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US Patent 7303953 Production of an integrated capacitor
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US Patent 7304387 Semiconductor integrated circuit device
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US Patent 7306989 Fabricating method of semiconductor device
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US Patent 7312097 Method of fabricating an optical concentrator for a photovoltaic solar cell
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US Patent 7312112 Transistor array substrate fabrication for an LCD
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US Patent 7312145 Electronic member, method for making the same, and semiconductor device
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US Patent 7314805 Method for fabricating semiconductor device
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US Patent 7315058 Semiconductor memory device having a floating gate
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US Patent 7316963 Method for manufacturing semiconductor device
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US Patent 7316964 Active matrix substrate, a manufacturing method of the active matrix substrate
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US Patent 7317203 Method and monitor structure for detecting and locating IC wiring defects
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US Patent 7323729 Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing precursor and products thereof and apparatus therefor
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US Patent 7326615 Method for manufacturing electronic non-volatile memory devices integrated in a semiconductor substrate
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US Patent 7326617 Method of fabricating a three-dimensional multi-gate device
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US Patent 7329620 System and method for providing an integrated circuit having increased radiation hardness and reliability
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US Patent 7329927 Integrated circuit devices having uniform silicide junctions
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US Patent 7335535 Method and apparatus for lubricating microelectromechanical devices in packages
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US Patent 7335995 Microelectronic assembly having array including passive elements and interconnects
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US Patent 7336530 CMOS pixel with dual gate PMOS
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US Patent 7338898 MOS transistor and fabrication thereof
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US Patent 7339226 Dual-level stacked flash memory cell with a MOSFET storage transistor
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US Patent 7341879 Method of manufacturing a point source light-emitting diode
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US Patent 7341939 Method for patterning micro features by using developable bottom anti-reflection coating
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US Patent 7341961 Method of manufacturing thin film transistor, thin film transistor manufactured using the method, and flat panel display device comprising the thin film transistor
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US Patent 7345305 Control of liner thickness for improving thermal cycle reliability
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US Patent 7348189 Field transistor monitoring pattern for shallow trench isolation defects in semiconductor device
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US Patent 7348676 Semiconductor device having a metal wiring structure
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US Patent 7352036 Semiconductor power device having a top-side drain using a sinker trench
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US Patent 7354851 Method for fabricating semiconductor device
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US Patent 7354852 Method of forming interconnection in semiconductor device
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US Patent 7355285 Structure of mounting electronic component
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US Patent 7358173 Bumping process of light emitting diode
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US Patent 7358588 Trench isolation type semiconductor device which prevents a recess from being formed in a field region
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US Patent 7361548 Methods of forming a capacitor using an atomic layer deposition process
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US Patent 7361614 Method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry
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US Patent 11183614 Semiconductor device
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US Patent 7365004 Method for manufacturing semiconductor device
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US Patent 7368313 Method of making a differential pressure sensor
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US Patent 7371592 Manufacturing method of thin film transistor array panel using an optical mask
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US Patent 7371629 N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications
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US Patent 7371698 Method of forming film pattern, active matrix substrate, electro-optic device, and electronic apparatus
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US Patent 7378729 Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom
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US Patent 7381615 Methods for self-aligned trench filling with grown dielectric for high coupling ratio in semiconductor devices
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US Patent 7382036 Doped single crystal silicon silicided eFuse
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US Patent 7384819 Method of forming stackable package
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US Patent 7384853 Method of performing salicide processes on MOS transistors
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US Patent 7385294 Semiconductor device having nickel silicide and method of fabricating nickel silicide
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US Patent 7387937 Thermal dissipation structures for FinFETs
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US Patent 7388243 Self-Aligned buried contact pair
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US Patent 7388257 Multi-gate device with high k dielectric for channel top surface
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US Patent 7390729 Method of fabricating a semiconductor device
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US Patent 7390741 Method for fabricating semiconductor device
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US Patent 7390755 Methods for post etch cleans
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US Patent 7393213 Method for material growth of GaN-based nitride layer
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US Patent 7393744 Method of manufacturing dielectric film of flash memory device
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US Patent 7393763 Manufacturing method of monocrystalline gallium nitride localized substrate
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US Patent 7396754 Method of making wafer level ball grid array
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US Patent 7397105 Apparatus to passivate inductively or capacitively coupled surface currents under capacitor structures
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US Patent 7397113 Semiconductor device
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US Patent 7400000 Nitride-based semiconductor device
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US Patent 7402493 Method for forming non-volatile memory devices
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US Patent 7402498 Methods of forming trench isolation regions
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US Patent 7402511 Configuration for testing the bonding positions of conductive drops and test method for using the same
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US Patent 7402886 Memory with self-aligned trenches for narrow gap isolation regions
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US Patent 7405151 Method for forming a semiconductor device
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US Patent 7405160 Method of making semiconductor device
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US Patent 7407856 Method of manufacturing a memory device
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US Patent 7407873 Method of manufacturing semiconductor device
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US Patent 7411210 Semiconductor probe with resistive tip having metal shield thereon
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US Patent 7411237 Lanthanum hafnium oxide dielectrics
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US Patent 7411276 Photosensitive device
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US Patent 7413977 Method of manufacturing semiconductor device suitable for forming wiring using damascene method
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US Patent 7414308 Integrated circuit with offset pins
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US Patent 7416956 Self-aligned trench filling for narrow gap isolation regions
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US Patent 7417276 Thin film capacitor and fabrication method thereof
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US Patent 7419550 Oxidizing method and oxidizing unit of object for object to be processed
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US Patent 7419877 Methods of fabricating silicon carbide devices including multiple floating guard ring edge termination
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US Patent 7419920 Metal thin film and semiconductor comprising a metal thin film
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US Patent 7420200 Damascene phase change memory
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US Patent 7420273 Thinned die integrated circuit package
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US Patent 7422964 Manufacturing method of the active matrix substrate, and an electro-optical apparatus having the active matrix substrate
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US Patent 7425466 Wire bonding system and method of use
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US Patent 7427527 Method for aligning devices
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US Patent 7427553 Fabricating method of semiconductor device
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US Patent 7427564 Method for forming storage node contact plug in semiconductor device
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US Patent 7427811 Semiconductor substrate
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US Patent 7429541 Method of forming trench isolation in the fabrication of integrated circuitry
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US Patent 7429766 Split gate type nonvolatile memory device
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US Patent 7432139 Methods for forming dielectrics and metal electrodes
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US Patent 7432168 Method for fabricating semiconductor device with thin gate spacer
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US Patent 7432174 Methods for fabricating semiconductor substrates with silicon regions having differential crystallographic orientations
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US Patent 7432190 Semiconductor device and manufacturing method thereof to prevent a notch
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US Patent 7432192 Post ECP multi-step anneal/H
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US Patent 7432541 Metal oxide semiconductor field effect transistor
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US Patent 7432567 Metal gate CMOS with at least a single gate metal and dual gate dielectrics
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US Patent 7435624 Method of reducing mechanical stress on a semiconductor die during fabrication
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US Patent 7435636 Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods
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US Patent 7435648 Methods of trench and contact formation in memory cells
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US Patent 7436019 Non-volatile memory cells shaped to increase coupling to word lines
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US Patent 7439094 Method of manufacturing a semiconductor package
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US Patent 7439173 Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via
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US Patent 7439192 Method of forming a layer on a semiconductor substrate
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US Patent 7439604 Method of forming dual gate dielectric layer
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US Patent 7442638 Method for forming a tungsten interconnect structure with enhanced sidewall coverage of the barrier layer
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US Patent 7443030 Thin silicon based substrate
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US Patent 7445998 Method for fabricating semiconductor device
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US Patent 7449359 Fabricating method of CMOS image sensor
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US Patent 7449390 Methods of forming memory
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US Patent 7452741 Process for manufacturing an apparatus that protects features during the removal of sacrificial materials
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US Patent 7456115 Method for forming semiconductor devices having reduced gate edge leakage current
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US Patent 7456434 Micro optical bench structure
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US Patent 7459377 Method for dividing substrate
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US Patent 7459391 Semiconductor device and method of fabricating the same
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US Patent 7462536 Method of forming bit line of semiconductor memory device
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US Patent 7462558 Method for fabricating a circuit component
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US Patent 7462563 Method of forming an etch indicator layer for reducing etch non-uniformities
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US Patent 7462918 Pressure sensor having gold-silicon eutectic crystal layer interposed between contact layer and silicon substrate
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US Patent 7465662 Method of making semiconductor device
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US Patent 7468305 Forming pocket and LDD regions using separate masks
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US Patent 7473591 Transistor with strain-inducing structure in channel
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US Patent 7473612 Method for fabricating a variable-resistance element including heating a RMCoO
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US Patent 7473618 Temporary structure to reduce stress and warpage in a flip chip organic package
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US Patent 7473651 Method of manufacturing carbon nanotube semiconductor device
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US Patent 7473936 Light emitting diodes (LEDs) with improved light extraction by roughening
‌
US Patent 7476587 Method for making a self-converged memory material element for memory cell
‌
US Patent 7479432 CMOS transistor junction regions formed by a CVD etching and deposition sequence
‌
US Patent 7479437 Method to reduce contact resistance on thin silicon-on-insulator device
‌
US Patent 7479462 Thin films and methods for the preparation thereof
‌
US Patent 7482668 Semiconductor device
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US Patent 7485531 Fabricating method of a non-volatile memory
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US Patent 7485948 Front-end processing of nickel plated bond pads
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US Patent 7488620 Method of fabricating leadframe based flash memory cards including singulation by straight line cuts
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US Patent 7489003 Semiconductor device having a channel extending vertically
‌
US Patent 7491634 Methods for forming roughened surfaces and applications thereof
‌
US Patent 7494867 Semiconductor device having MIM capacitive elements and manufacturing method for the same
‌
US Patent 7494902 Method of fabricating a strained multi-gate transistor
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US Patent 7495313 Germanium substrate-type materials and approach therefor
‌
US Patent 7498212 Laser annealing method and semiconductor device fabricating method
‌
US Patent 7498271 Nitrogen based plasma process for metal gate MOS device
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US Patent 7498630 Nonvolatile semiconductor memory
‌
US Patent 7501351 Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
‌
US Patent 7504320 Method for manufacturing a tag integrated circuit flexible board
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US Patent 7504336 Methods for forming CMOS devices with intrinsically stressed metal silicide layers
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US Patent 7504728 Integrated circuit having bond pad with improved thermal and mechanical properties
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US Patent 7504731 Interconnect structure to reduce stress induced voiding effect
‌
US Patent 7507623 Fabricating method of semiconductor device
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US Patent 7507628 Method of manufacturing a non-volatile memory device
‌
US Patent 7507654 Method for mounting electronic element on a circuit board
‌
US Patent 7507663 Fabrication of semiconductor devices
‌
US Patent 7508018 Image sensor having a highly doped and shallow pinning layer
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US Patent 7511374 Microelectronic imaging units having covered image sensors
‌
US Patent 7514321 Method of making three dimensional NAND memory
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US Patent 7514352 Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases
‌
US Patent 7514734 Hardmask for forming ferroelectric capacitors in a semiconductor device and methods for fabricating the same
‌
US Patent 7514788 Structure of mounting electronic component
‌
US Patent 11189433 Multifunctional solid-state devices for solar control, photovoltaic conversion and artificial lighting
‌
US Patent 11189664 Radiation detection device comprising organic photodiodes
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US Patent 11189802 Organic electroluminescent element
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US Patent 11189803 Organic electroluminescent element and electronic device containing the organic electroluminescent element
‌
US Patent 11191162 Circuit board supporting structure and light emitting device having the same
‌
US Patent 7518142 Encapsulation for organic device
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US Patent 7521280 Method for forming an optical image sensor with an integrated metal-gate reflector
‌
US Patent 7521338 Method for sawing semiconductor wafer
‌
US Patent 7521344 Method of forming semiconductor compound film for fabrication of electronic device and film produced by same using a solid solution
‌
US Patent 7521712 Thin film semiconductor device
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US Patent 7524686 Method of making light emitting diodes (LEDs) with improved light extraction by roughening
‌
US Patent 7528001 Method of manufacturing a CMOS image sensor
‌
US Patent 7531394 Manufacturing method for a TFT LCD array substrate
‌
US Patent 7534646 Method of fabricating an organic field transistor
‌
US Patent 7534703 Method for bonding semiconductor chip
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US Patent 7534725 Advanced process control for semiconductor processing
‌
US Patent 7537995 Method for fabricating a dual poly gate in semiconductor device
‌
US Patent 7538343 Organic light emitting display (OLED)
‌
US Patent 7538409 Semiconductor devices
‌
US Patent 7538432 Temporary structure to reduce stress and warpage in a flip chip organic package
‌
US Patent 7541260 Trench diffusion isolation in semiconductor devices
‌
US Patent 7541288 Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques
‌
US Patent 7544592 Method for increasing etch rate during deep silicon dry etch
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US Patent 7545034 Thermal energy removal structure and method
‌
US Patent 7547604 Method of forming a recessed gate structure on a substrate having insulating columns and removing said insulating columns after forming a conductive region of the gate structure
‌
US Patent 7547610 Method of making a semiconductor device comprising isolation trenches inducing different types of strain
‌
US Patent 7550384 Semiconductor device and method for forming pattern in the same
‌
US Patent 7553730 Methods of fabrication employing nanoscale mandrels
‌
US Patent 7553752 Method of making a wafer level integration package
‌
US Patent 7553755 Method for symmetric deposition of metal layer
‌
US Patent 7557405 High-density nonvolatile memory
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US Patent 7560339 Nonvolatile memory cell comprising a reduced height vertical diode
‌
US Patent 7560789 Semiconductor device
‌
US Patent 7563625 Method of making light-emitting diodes (LEDs) with improved light extraction by roughening
‌
US Patent 7563689 Method for fabricating nonvolatile memory device
‌
US Patent 7563712 Method of forming micro pattern in semiconductor device
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US Patent 7564093 Semiconductor device
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US Patent 7566579 Method of fabricating semiconductor devices with a multi-role facilitation layer
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US Patent 7566628 Process for making a resistive memory cell with separately patterned electrodes
‌
US Patent 7566940 Electromechanical devices having overlying support structures
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US Patent 7569410 Method for integrated MEMS packaging
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US Patent 7569457 Method of fabricating semiconductor device
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US Patent 7569488 Methods of making a MEMS device by monitoring a process parameter
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US Patent 7569492 Method for post-etch cleans
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US Patent 7572722 Method of fabricating nickel silicide
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US Patent 7575974 Method for fabricating semiconductor device including recess gate
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US Patent 7575989 Method of manufacturing a transistor of a semiconductor device
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US Patent 7582494 Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses
‌
US Patent 7582949 Semiconductor devices
‌
US Patent 7585690 Process for producing group III nitride compound semiconductor light emitting device, group III nitride compound semiconductor light emitting device and lamp
‌
US Patent 7585778 Method of etching an organic low-k dielectric material
‌
US Patent 7589006 Method for manufacturing semiconductor device
‌
US Patent 7589404 Semiconductor device
‌
US Patent 7589424 Thin silicon based substrate
‌
US Patent 7592272 Manufacturing method of semiconductor integrated circuit
‌
US Patent 7595215 CMOS image sensor and method for manufacturing the same
‌
US Patent 7595254 Method of manufacturing a semiconductor device
‌
US Patent 7598154 Manufacturing method of semiconductor device
‌
US Patent 7598160 Method for manufacturing thin film semiconductor
‌
US Patent 7598165 Methods for forming a multiplexer of a memory device
‌
US Patent 7598171 Method of manufacturing a semiconductor device
‌
US Patent 7601984 Field effect transistor with amorphous oxide active layer containing microcrystals and gate electrode opposed to active layer through gate insulator
‌
US Patent 7601986 Epitaxial semiconductor structures having reduced stacking fault nucleation sites
‌
US Patent 7605014 Method of fabricating resistive probe having self-aligned metal shield
‌
US Patent 7611963 Method for forming a multi-layer shallow trench isolation structure in a semiconductor device
‌
US Patent 7612422 Structure for dual work function metal gate electrodes by control of interface dipoles
‌
US Patent 7612427 Apparatus for confining inductively coupled surface currents
‌
US Patent 7615458 Activation of CMOS source/drain extensions by ultra-high temperature anneals
‌
US Patent 7615484 Integrated circuit manufacturing method using hard mask
‌
US Patent 7618859 Thin film capacitor and fabrication method thereof
‌
US Patent 7622308 Process control using process data and yield data
‌
US Patent 7622356 Method of fabricating metal oxide semiconductor field effect transistor
‌
US Patent 7622390 Method for treating a dielectric film to reduce damage
‌
US Patent 7622738 Display device having a multi-layer conductive layer and manufacturing method therefore
‌
US Patent 7625767 Methods of making spintronic devices with constrained spintronic dopant
‌
US Patent 7626253 Computing device including a stacked semiconductor device
‌
US Patent 7629195 Method of making light emitting diodes (LEDs) with improved light extraction by roughening
‌
US Patent 7629196 Method for manufacturing an integrated circuit having increased radiation hardness and reliability
‌
US Patent 7629255 Method for reducing microloading in etching high aspect ratio structures
‌
US Patent 7632699 Method for manufacturing CMOS image sensor
‌
US Patent 7632761 Method of making thin film anatase titanium dioxide
‌
US Patent 7635627 Methods for fabricating a memory device including a dual bit memory cell
‌
US Patent 7638410 Method of transferring strained semiconductor structure
‌
US Patent 7638422 Method of manufacturing metal insulating layer in semiconductor device
‌
US Patent 7642106 Methods for identifying an allowable process margin for integrated circuits
‌
US Patent 7642190 Method of forming thin insulating layer in MRAM device
‌
US Patent 7645705 Method of fabricating a semiconductor device having a pre metal dielectric liner
‌
US Patent 7645709 Methods for low temperature oxidation of a semiconductor device
‌
US Patent 7646080 Protective film structure
‌
US Patent 7648870 Method of forming fuse region in semiconductor damascene process
‌
US Patent 7651920 Noise reduction in semiconductor device using counter-doping
‌
US Patent 7651946 Wet etch processing
‌
US Patent 7655526 Method for manufacturing semiconductor device
‌
US Patent 7659138 Method for manufacturing an organic semiconductor element
‌
US Patent 7659146 Manufacturing method of semiconductor device
‌
US Patent 7659184 Plasma immersion ion implantation process with chamber seasoning and seasoning layer plasma discharging for wafer dechucking
‌
US Patent 7659591 Apparatus having a layer of material configured as a reservoir having an interior capable of holding a liquid
‌
US Patent 7659630 Interconnect structures with interlayer dielectric
‌
US Patent 7662709 Surface mounting method
‌
US Patent 7662728 Substrate processing method
‌
US Patent 7666732 Method of fabricating a metal gate CMOS with at least a single gate metal and dual gate dielectrics
‌
US Patent 7666735 Method for forming semiconductor devices with active silicon height variation
‌
US Patent 7666778 Method of arranging solder balls for ball grid array packages
‌
US Patent 7666784 Methods of trench and contact formation in memory cells
‌
US Patent 7670712 Metal oxynitride electrode catalyst
‌
US Patent 7671411 Lateral double-diffused MOSFET transistor with a lightly doped source
‌
US Patent 7674704 Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases
‌
US Patent 7674724 Oxidizing method and oxidizing unit for object to be processed
‌
US Patent 7678683 Method of fabricating copper damascene and dual damascene interconnect wiring
‌
US Patent 7682972 Advanced multilayer coreless support structures and method for their fabrication
‌
US Patent 7687290 Method for manufacturing semiconductor optical device
‌
US Patent 7687865 Method and structure to reduce contact resistance on thin silicon-on-insulator device
‌
US Patent 7691660 Methods of manufacturing microelectronic imaging units on a microfeature workpiece
‌
US Patent 7691706 Method of fabricating a semiconductor device
‌
US Patent 7691737 Copper process methodology
‌
US Patent 7691740 Semiconductor device and method of fabricating same
‌
US Patent 7692284 Package using array capacitor core
‌
US Patent 7696027 Method of fabricating display substrate and method of fabricating display panel using the same
‌
US Patent 7696041 Method for fabricating a semiconductor component and semiconductor component
‌
US Patent 7700435 Method for fabricating deep trench DRAM array
‌
US Patent 7700469 Methods of forming semiconductor constructions
‌
US Patent 7700949 Thin film transistor array substrate, method for manufacturing the same, liquid crystal display having the substrate, and method for manufacturing the liquid crystal display
‌
US Patent 7704848 Method for designing semiconductor device and semiconductor device
‌
US Patent 7704874 Method for fabricating a frontside through-wafer via in a processed wafer and related structure
‌
US Patent 7704877 Method of manufacturing semiconductor device and control system
‌
US Patent 7704891 Method of producing semiconductor device
‌
US Patent 7705407 High voltage semicondutor transistor device having small size and long electron flow path
‌
US Patent 7705461 Structure of tag integrated circuit flexible board
‌
US Patent 7709329 High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications
‌
US Patent 7709840 Bottom gate thin film transistor, flat panel display having the same and method of fabricating the same
‌
US Patent 7709902 Metal gate CMOS with at least a single gate metal and dual gate dielectrics
‌
US Patent 7713815 Semiconductor device including a vertical decoupling capacitor
‌
US Patent 7713846 Process applied to semiconductor
‌
US Patent 7713862 Printed wiring board and method for manufacturing the same
‌
US Patent 7714376 Non-volatile memory device with polysilicon spacer and method of forming the same
‌
US Patent 7719041 MIM capacitor high-k dielectric for increased capacitance density
‌
US Patent 7719055 Cascode power switch topologies
‌
US Patent 7723165 Method of forming component package
‌
US Patent 7727797 Method for manufacturing organic thin film transistor substrate
‌
US Patent 7727856 Selective STI stress relaxation through ion implantation
‌
US Patent 7727862 Semiconductor device including semiconductor constituent and manufacturing method thereof
‌
US Patent 7727875 Grooving bumped wafer pre-underfill system
‌
US Patent 7728325 Display device
‌
US Patent 7728387 Semiconductor device with high on current and low leakage
‌
US Patent 7728394 Semiconductor device and manufacturing method thereof
‌
US Patent 7732239 Method for manufacturing solid-state image sensor
‌
US Patent 7732259 Non-leaded semiconductor package and a method to assemble the same
‌
US Patent 7732321 Method for shielding integrated circuits
‌
US Patent 7732876 Power transistor with trench sinker for contacting the backside
‌
US Patent 7736747 Silicon parts joined by a silicon layer preferably plasma sprayed
‌
US Patent 7736991 Method of forming isolation layer of semiconductor device
‌
US Patent 7737512 Integrated circuit devices having uniform silicide junctions
‌
US Patent 7737544 Sensor system having a substrate and a housing, and method for manufacturing a sensor system
‌
US Patent 7737564 Power configuration method for structured ASICs
‌
US Patent 7745286 Methods of forming semiconductor devices
‌
US Patent 7749854 Method for making a self-converged memory material element for memory cell
‌
US Patent 7749867 Method of cutting processed object
‌
US Patent 7749889 Manufacturing method of semiconductor device
‌
US Patent 7749904 Method of forming a dual damascene structure
‌
US Patent 7754598 Method for manufacturing coreless packaging substrate
‌
US Patent 7755142 Thin-film transistor and image display device
‌
US Patent 7755161 Semiconductor devices
‌
US Patent 7759207 Integrated circuit system employing stress memorization transfer
‌
US Patent 7759669 Phase change memory element with phase-change electrodes
‌
US Patent 7763967 Semiconductor device with surface mounting terminals
‌
US Patent 7768071 Stabilizing breakdown voltages by forming tunnels for ultra-high voltage devices
‌
US Patent 7772067 Methods of forming phase-changeable memory devices using growth-enhancing and growth-inhibiting layers for phase-changeable materials
‌
US Patent 7772078 Germanium substrate-type materials and approach therefor
‌
US Patent 7776638 Two epitaxial layers to reduce crosstalk in an image sensor
‌
US Patent 7779785 Production method for semiconductor device and substrate processing apparatus
‌
US Patent 7785943 Method for forming a multi-gate device with high k dielectric for channel top surface
‌
US Patent 7785948 Semiconductor element and process for producing the same
‌
US Patent 7786547 Formation of active area using semiconductor growth process without STI integration
‌
US Patent 7786574 Microelectronic imaging units
‌
US Patent 7786602 Patterned die attach and packaging method using the same
‌
US Patent 7790625 Method for manufacturing semiconductor device
‌
US Patent 7795093 Front-end processing of nickel plated bond pads
‌
US Patent 7795141 Method of manufacturing semiconductor device suitable for forming wiring using damascene method
‌
US Patent 7795149 Masking techniques and contact imprint reticles for dense semiconductor fabrication
‌
US Patent 7795715 Leadframe based flash memory cards
‌
US Patent 7799660 Method for manufacturing SOI substrate
‌
US Patent 7800225 Microelectronic die including locking bump and method of making same
‌
US Patent 7807586 Method of forming a stressed passivation film using a non-ionizing electromagnetic radiation-assisted oxidation process
‌
US Patent 7808012 Group of phosphor particles for light-emitting device, light-emitting device and backlight for liquid crystal display
‌
US Patent 7811885 Method for forming a phase change device
‌
US Patent 7811922 Method for manufacturing semiconductor device
‌
US Patent 7812394 CMOS transistor junction regions formed by a CVD etching and deposition sequence
‌
US Patent 7816224 Method for fabricating an ultra thin silicon on insulator
‌
US Patent 7816278 In-situ hybrid deposition of high dielectric constant films using atomic layer deposition and chemical vapor deposition
‌
US Patent 7816281 Method for manufacturing a semiconductor device
‌
US Patent 7820455 Method for manufacturing a tunnel junction magnetoresistive sensor with improved performance and having a CoFeB free layer
‌
US Patent 7821016 Light activated silicon controlled switch
‌
US Patent 7825475 Mixed voltage tolerant input/output electrostatic discharge devices
‌
US Patent 7829436 Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer
‌
US Patent 7829458 Method of forming a wiring structure in a semiconductor device
‌
US Patent 7829460 Method of manufracturing increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride
‌
US Patent 7833814 Method of forming pinned photodiode (PPD) pixel with high shutter rejection ratio for snapshot operating CMOS sensor
‌
US Patent 7833873 Method and structure to reduce contact resistance on thin silicon-on-insulator device
‌
US Patent 7834404 Semiconductor device
‌
US Patent 7838437 Method for simultaneous recrystallization and doping of semiconductor layers
‌
US Patent 7838965 ESD protected integrated capacitor with large capacity
‌
US Patent 7839002 Partially underfilled solder grid arrays
‌
US Patent 7842534 Method for forming a compound semi-conductor thin-film
‌
US Patent 7842549 Methods of fabricating silicon carbide devices incorporating multiple floating guard ring edge terminations
‌
US Patent 7843042 Wafer level integration package
‌
US Patent 7851307 Method of forming complex oxide nanodots for a charge trap
‌
US Patent 7851351 Manufacturing method for semiconductor devices with enhanced adhesivity and barrier properties
‌
US Patent 7851383 Method and system for forming a controllable gate oxide
‌
US Patent 7851806 Thin film transistor liquid crystal display array substrate and manufacturing method thereof
‌
US Patent 7851918 Three-dimensional package module
‌
US Patent 7855097 Method of increasing yield in OFETs by using a high-K dielectric layer in a dual dielectric layer
‌
US Patent 7855117 Method of forming a thin layer and method of manufacturing a semiconductor device
‌
US Patent 7855385 SiC crystal and semiconductor device
‌
US Patent 7858482 Method of forming a semiconductor device using stress memorization
‌
US Patent 7858509 High-dielectric film substrate processing method
‌
US Patent 7859023 Standard cell and semiconductor device including the same
‌
US Patent 7859060 Ultra thin silicon on insulator
‌
US Patent 7859096 Semiconductor device
‌
US Patent 7859104 Thermal interface material having carbon nanotubes and component package having the same
‌
US Patent 7863142 Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device
‌
US Patent 7863144 Semiconductor device and method for manufacturing the device
‌
US Patent 7863178 Method for manufacturing a GaN based optical device
‌
US Patent 7863193 Integrated circuit fabrication process using a compression cap layer in forming a silicide with minimal post-laser annealing dopant deactivation
‌
US Patent 7863685 Trench MOSFET with embedded junction barrier Schottky diode
‌
US Patent 7867895 Method of fabricating improved interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric
‌
US Patent 7868368 Complementary metal oxide semiconductor (CMOS) image sensor
‌
US Patent 7868467 Semiconductor device
‌
US Patent 7871853 Plasma doping method and apparatus employed in the same
‌
US Patent 7871912 Methods of making semiconductor-based electronic devices by forming freestanding semiconductor structures
‌
US Patent 7872312 Semiconductor device comprising a high dielectric constant insulating film including nitrogen
‌
US Patent 7875485 Methods of fabricating MEMS devices having overlying support structures
‌
US Patent 7880192 Nitride semiconductor light emitting element and nitride semiconductor light emitting device
‌
US Patent 7880253 Integrated optical filter
‌
US Patent 7884380 Semiconductor light emitting device
‌
US Patent 7888183 Thinned die integrated circuit package
‌
US Patent 7888222 Method of fabricating a lateral double-diffused MOSFET
‌
US Patent 7888226 Method of fabricating power semiconductor device for suppressing substrate recirculation current
‌
US Patent 7897441 Method of fabricating a CMOS image sensor
‌
US Patent 7897502 Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
‌
US Patent 7897959 Phase change memory device having a word line contact
‌
US Patent 7898011 Image sensor having anti-reflection film for reducing crosstalk
‌
US Patent 7898072 Package stacking system with mold contamination prevention
‌
US Patent 7901988 Method for forming a package-on-package structure
‌
US Patent 7902090 Method of forming a layer on a semiconductor substrate
‌
US Patent 7902636 Semiconductor chip including a substrate and multilayer part
‌
US Patent 7902674 Three-dimensional die-stacking package structure
‌
US Patent 7906400 Method of manufacturing a semiconductor device having transistors and semiconductor device having transistors
‌
US Patent 7910396 Three-stage formation of thin-films for photovoltaic devices
‌
US Patent 7910435 Method of manufacturing a semiconductor device having a channel extending vertically
‌
US Patent 7915086 Manufacturing method of semiconductor device
‌
US Patent 7915134 Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material
‌
US Patent 7915174 Dielectric stack containing lanthanum and hafnium
‌
US Patent 7915681 Transistor with reduced charge carrier mobility
‌
US Patent 7919381 Germanium substrate-type materials and approach therefor
‌
US Patent 7919863 Semiconductor constructions
‌
US Patent 7923297 Manufacturing method of semiconductor device
‌
US Patent 7923382 Method for forming roughened surface
‌
US Patent 7923736 Flat panel display
‌
US Patent 7932568 Microelectromechanical component
‌
US Patent 7935980 Method of manufacturing a semiconductor light-emitting device
‌
US Patent 7936018 Semiconductor device
‌
US Patent 7939376 Patterned die attach and packaging method using the same
‌
US Patent 7939817 Integrated circuit including memory element with spatially stable material
‌
US Patent 7939861 Non-volatile memory devices having floating-gates FETs with different source-gate and drain-gate border lengths
‌
US Patent 7939933 Semiconductor device
‌
US Patent 7943425 Semiconductor wafer sawing system and method
‌
US Patent 7943498 Method of forming micro pattern in semiconductor device
‌
US Patent 7943992 Metal gate structures with recessed channel
‌
US Patent 7947562 Noise reduction in semiconductor device using counter-doping
‌
US Patent 7948065 Integrated circuit having increased radiation hardness and reliability
‌
US Patent 7951648 Chip-level underfill method of manufacture
‌
US Patent 7955902 Manufacturing method of semiconductor device with surface mounting terminals
‌
US Patent 7955917 Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate methods
‌
US Patent 7955954 Method of making semiconductor devices employing first and second carriers
‌
US Patent 7955976 Methods of forming semiconductor structures
‌
US Patent 7956366 Monolithic light emitting device and driving method therefor
‌
US Patent 7960272 Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
‌
US Patent 7964894 Integrated circuit system employing stress memorization transfer
‌
US Patent 7964962 Method of manufacturing a semiconductor apparatus
‌
US Patent 7964973 Chip structure
‌
US Patent 7968449 Method for manufacturing printed wiring board
‌
US Patent 7968951 Interconnecting bit lines in memory devices for multiplexing
‌
US Patent 7972979 Substrate processing method and substrate processing apparatus
‌
US Patent 7973371 Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region
‌
US Patent 7973378 Solid-state imaging device having improved sensitivity and reduced flare
‌
US Patent 7977150 Method for manufacturing an organic semiconductor element
‌
US Patent 7977205 Method of forming isolation layer of semiconductor device
‌
US Patent 7977687 Light emitter device
‌
US Patent 7985674 SiH
‌
US Patent 7986010 High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications
‌
US Patent 7989245 Method for fabricating image sensor
‌
US Patent 7989261 Fabricating a gallium nitride device with a diamond layer
‌
US Patent 7989347 Process for filling recessed features in a dielectric substrate
‌
US Patent 7989822 Optocoupler using silicon based LEDs
‌
US Patent 7994584 Semiconductor device having non-silicide region in which no silicide is formed on diffusion layer
‌
US Patent 7994602 Titanium dioxide thin film systems
‌
US Patent 7995770 Apparatus and method for aligning and controlling reception of sound transmissions at locations distant from the sound source
‌
US Patent 7998812 Semiconductor device
‌
US Patent 8003459 Method for forming semiconductor devices with active silicon height variation
‌
US Patent 8003500 Plasma immersion ion implantation process with chamber seasoning and seasoning layer plasma discharging for wafer dechucking
‌
US Patent 8003547 Method of manufacturing semiconductor device
‌
US Patent 8004033 High-density nonvolatile memory
‌
US Patent 8004036 MOSFET-Schottky rectifier-diode integrated circuits with trench contact structures for device shrinkage and performance improvement
‌
US Patent 8008176 Masked ion implant with fast-slow scan
‌
US Patent 8008208 Method of cleaning and forming a negatively charged passivation layer over a doped region
‌
US Patent 8008737 Semiconductor device
‌
US Patent 8008744 Selective STI stress relaxation through ion implantation
‌
US Patent 8008784 Package including a lead frame, a chip and a sealant
‌
US Patent 8012775 Method of forming a light activated silicon controlled switch
‌
US Patent 8012843 Optimized halo or pocket cold implants
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